AD7942BRMZ Analog Devices Inc, AD7942BRMZ Datasheet - Page 21

• Manufacturer Part Number: AD7942BRMZ
• Description: IC ADC 14BIT 250KSPS 10-MSOP
• Manufacturer: Analog Devices Inc
• Series: PulSAR®r

Specifications of AD7942BRMZ

• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Bits: 14
• Sampling Rate (per Second): 250k
• Number Of Converters: 1
• Power Dissipation (max): 1.25mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 10-TFSOP (0.118", 3.00mm Width)
• Resolution (bits): 14bit
• Sampling Rate: 250kSPS
• Input Channel Type: Pseudo Differential
• Supply Voltage Range - Analog: 2.3V To 5.5V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-AD7942CB - BOARD EVALUATION FOR AD7942
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Chain Mode Without Busy Indicator
This mode can be used to daisy-chain multiple AD7942s on
a 3-wire serial interface. This feature is useful for reducing
component count and wiring connections, for example, in
isolated multiconverter applications or for systems with a
limited interfacing capacity. Data readback is analogous to
clocking a shift register. A connection diagram example using
two AD7942s is shown in Figure 38 and the corresponding
timing diagram is given in Figure 39.
When SDI and CNV are low, SDO is driven low. With SCK
low, a rising edge on CNV initiates a conversion, selects the
chain mode, and disables the busy indicator. In this mode, CNV
is held high during the conversion phase and the subsequent
data readback. When the conversion is complete, the MSB is
output onto SDO and the AD7942 enters the acquisition phase
SDO
ACQUISITION
SDI
A
t
= SDI
HSCKCNV
CNV
SCK
SDO
A
= 0
B
B
CONVERSION
t
SSCKCNV
t
CONV
t
EN
SDI
t
t
AD7942
HSDO
DSDO
Figure 39. Chain Mode Without Busy Indicator, Serial Interface Timing
CNV
SCK
Figure 38. Chain Mode Without Busy Indicator Connection Diagram
A
D
D
1
A
B
13
13
t
SSDISCK
SDO
D
D
2
A
B
12
12
D
D
3
A
B
11
11
Rev. B | Page 21 of 24
t
SCKL
SDI
t
HSDISCK
12
AD7942
CNV
SCK
B
t
D
D
13
CYC
A
B
and powers down. The remaining data bits stored in the inter-
nal shift register are then clocked by subsequent SCK falling
edges. For each ADC, SDI feeds the input of the internal shift
register and is clocked by the SCK falling edge. Each ADC in
the chain outputs its data MSB first and 14 × N clocks are
required to readback the N ADCs. The data is valid on both
SCK edges. Although the rising edge can be used to capture
the data, a digital host also using the SCK falling edge allows
a faster reading rate and consequently more AD7942s in the
chain, provided the digital host has an acceptable hold time.
The maximum conversion rate may be reduced due to the total
readback time. For instance, with a 5 ns digital host setup time
and 3 V interface, up to eight AD7942s running at a conversion
rate of 220 kSPS can be daisy-chained on a 3-wire port.
1
1
ACQUISITION
SDO
t
SCK
t
t
SCKH
D
D
ACQ
14
A
B
0
0
D
15
A
13
CONVERT
DATA IN
CLK
D
DIGITAL HOST
16
A
12
26
D
27
A
1
D
28
A
0
AD7942