AD7730LBRU Analog Devices Inc, AD7730LBRU Datasheet
AD7730LBRU
Specifications of AD7730LBRU
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AD7730LBRU Summary of contents
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KEY FEATURES Resolution of 230,000 Counts (Peak-to-Peak) Offset Drift: 5 nV/ C Gain Drift: 2 ppm/ C Line Frequency Rejection: >150 dB Buffered Differential Inputs Programmable Filter Cutoffs Specified for Drift Over Time Operates with Reference Voltages of 1 ...
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AD7730–SPECIFICATIONS Parameter STATIC PERFORMANCE (CHP = Missing Codes 2 Output Noise and Update Rates Integral Nonlinearity 2 Offset Error 2 Offset Drift vs. Temperature 4 Offset Drift vs. Time 2, 5 Positive Full-Scale Error ...
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Parameter LOGIC INPUTS Input Current All Inputs Except SCLK and MCLK Input Low Voltage INL V , Input Low Voltage INL V , Input High Voltage INH SCLK Only (Schmitt Triggered Input ...
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AD7730/AD7730L NOTES 11 Temperature range: – + Sample tested during initial release. 13 The offset (or zero) numbers with CHP = 1 are typically 3 V precalibration. Internal zero-scale calibration reduces this by about 1 V. ...
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... Model AD7730BN AD7730BR AD7730BRU EVAL-AD7730EB AD7730LBR AD7730LBRU EVAL-AD7730LEB Figure 1. Load Circuit for Access Time and Bus Relinquish Time CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. ...
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AD7730/AD7730L BUFFER AMPLIFIER THE BUFFER AMPLIFIER PRESENTS A HIGH IMPEDANCE INPUT STAGE FOR THE ANALOG INPUTS ALLOWING SIGNIFICANT EXTERNAL SOURCE IMPEDANCES SEE PAGE 24 BURNOUT CURRENTS TWO 100nA BURNOUT CURRENTS ALLOW THE USER TO EASILY DETECT ...
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INPUT CHOPPING THE ANALOG INPUT TO THE PART CAN BE CHOPPED. IN CHOPPING MODE, WITH AC EXCITATION DISABLED, THE INPUT CHOPPING IS INTERNALTO THE DEVICE. IN CHOPPING MODE, WITH AC EXCITATION ENABLED, THE CHOPPING IS ASSUMED TO BE PERFORMED EXTERNAL ...
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AD7730/AD7730L Pin No. Mnemonic Function 3 MCLK OUT When the master clock for the device is a crystal/resonator, the crystal/resonator is connected between MCLK IN and MCLK OUT external clock is applied to the MCLK IN, MCLK OUT ...
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Pin No. Mnemonic Function STANDBY 18 Logic Input. Taking this pin low shuts down the analog and digital circuitry, reducing current consumption to the 5 A range. The on-chip registers retain all their values when the part is in standby ...
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AD7730/AD7730L OUTPUT NOISE AND RESOLUTION SPECIFICATION The AD7730 can be programmed to operate in either chop mode or nonchop mode. The chop mode can be enabled in ac-excited or dc-excited applications optional in dc-excited applications, but chop mode ...
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Table III. Output Noise vs. Input Range and Update Rate (CHP = 0) Output – Settling Time Data Rate Frequency Word Normal Mode 150 Hz 5.85 Hz 2048 166 ms 200 Hz 7.8 Hz 1536 125 ms 300 ...
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AD7730/AD7730L Register Name Type Size Communications Write Only 8 Bits Register WEN ZERO RW1 RW0 ZERO Status Register Read Only 8 Bits RDY STDY STBY NOREF MS3 Data Register Read Only 16 Bits or 24 Bits Mode Register Read/Write 16 ...
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Communications Register (RS2–RS0 = The Communications Register is an 8-bit write-only register. All communications to the part must start with a write operation to the Communications Register. The data written to the Communications Register determines whether the ...
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AD7730/AD7730L Bit Bit Location Mnemonic Description CR3 ZERO A zero must be written to this bit to ensure correct operation of the AD7730. CR2–CR0 RS2–RS0 Register Selection Bits. RS2 is the MSB of the three selection bits. The three bits ...
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Data Register (RS2–RS0 = 0, 0, 1); Power On/Reset Status: 000000 Hex The Data Register on the part is a read-only register which contains the most up-to-date conversion result from the AD7730. Fig- ure 5 shows a flowchart for reading ...
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AD7730/AD7730L MD2 MD1 MD0 Operating Mode Sync (Idle) Mode. In this mode, the modulator and filter are held in reset mode and the AD7730 is not processing any new samples or data. Placing the part in this ...
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Bit Bit Location Mnemonic Description MR12 B/U Bipolar/Unipolar Bit this bit selects bipolar operation and the output coding 000 for negative full-scale input 000 for zero input, and ...
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AD7730/AD7730L Bit Bit Location Mnemonic Description MR2 BO Burnout Current Bit this bit activates the burnout currents. When active, the burnout currents connect to the selected analog input pair, one source current to the AIN(+) input and ...
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CHOP SKIP Bit Bit Location Mnemonic Description FR11–FR10 ZERO A zero must be written to these bits to ensure correct operation of the AD7730. FR9 SKIP FIR Filter Skip Bit. With a ...
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AD7730/AD7730L DAC Register (RS2–RS0 = 1, 0, 0); Power On/Reset Status: 20 Hex The DAC Register is an 8-bit register from which data can either be read or to which data can be written. This register provides the code for ...
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READING FROM AND WRITING TO THE ON-CHIP REGISTERS The AD7730 contains a total of thirteen on-chip registers. These registers are all accessed over a three-wire interface result, addressing of registers is via a write operation to the topmost ...
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AD7730/AD7730L CALIBRATION OPERATION SUMMARY The AD7730 contains a number of calibration options as outlined previously. Table XVII summarizes the calibration types, the operations involved and the duration of the operations. There are two methods of determining the end of calibration. ...
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CIRCUIT DESCRIPTION The AD7730 is a sigma-delta A/D converter with on-chip digital filtering, intended for the measurement of wide dynamic range, low-frequency signals such as those in weigh-scale, strain-gage, pressure transducer or temperature measurement applications. It contains a sigma-delta (or ...
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AD7730/AD7730L ANALOG INPUT Analog Input Channels The AD7730 contains two differential analog input channels, a primary input channel, AIN1, and a secondary input channel, AIN2. The input pairs provide programmable gain, differential channels which can handle either unipolar or bipolar ...
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Burnout Currents The AD7730 contains two 100 nA constant current generators, one source current from AV to AIN(+) and one sink current DD from AIN(–) to AGND. The currents are switched to the se- lected analog input pair. Both currents ...
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AD7730/AD7730L If the AD7730 is performing either an offset or gain calibration and the NOREF bit becomes active, the updating of the respec- tive calibration register is inhibited to avoid loading incorrect coefficients to this register. If the user is ...
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Chop Mode With chop mode enabled on the AD7730, the signal processing chain is synchronously chopped at the analog input and at the output of the first stage filter. This means that for each output of the first stage filter ...
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AD7730/AD7730L Because of this effect, care should be taken in choosing an out- put rate that is close to the line frequency in the application. If the line frequency is 50 Hz, an output update rate should ...
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FASTStep Mode The second mode of operation of the second stage filter is in FASTStep mode which enables it to respond rapidly to step FASTStep inputs. This mode is enabled by placing the FAST bit of the ...
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AD7730/AD7730L Internally in the AD7730, the coefficients are normalized before being used to scale the words coming out of the digital filter. The offset calibration register contains a value which, when normalized, is subtracted from all conversion results. The gain ...
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MD2, MD1, MD0 bits of the Mode Register to initiate a conversion. If RDY is low before (or goes low during) the calibration com- mand write to ...
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AD7730/AD7730L The range of input span in both the unipolar and bipolar modes has a minimum value of 0.8 FS and a maximum value of 2.1 FS. However, the span (which is the difference between the bottom of the AD7730’s ...
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MCLK IN C1 CRYSTAL OR CERAMIC RESONATOR MCLK OUT C2 Figure 17. Crystal/Resonator Connections The on-chip oscillator circuit also has a start-up time associated with it before it has attained its correct frequency and correct voltage levels. The typical start-up ...
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AD7730/AD7730L POWER SUPPLIES There is no specific power sequence required for the AD7730, either the AV or the DV supply can come up first. While DD DD the latch-up performance of the AD7730 is very good important that ...
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SERIAL INTERFACE The AD7730’s programmable functions are controlled via a set of on-chip registers. Access to these registers is via the part’s serial interface. After power-on or RESET, the device expects a write to its Communications Register. The data written ...
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AD7730/AD7730L In DSP applications, the SCLK is generally a continuous clock. In these applications, the CS input for the AD7730 is generated from a frame synchronization signal from the DSP. In these applications, the first edge after CS goes low ...
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CONFIGURING THE AD7730 The AD7730 contains twelve on-chip registers that can be accessed via the serial interface. Figure 5 and Figure 6 have outlined a flowchart for the reading and writing of these registers. Table XIX and Table XX outline ...
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AD7730/AD7730L MICROCOMPUTER/MICROPROCESSOR INTERFACING The AD7730’s flexible serial interface allows for easy interface to most microcomputers and microprocessors. The pseudo-code of Table XIX and Table XX outline typical sequences for inter- facing a microcontroller or microprocessor to the AD7730. Figures 20, ...
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The serial clock on the 8XC51 idles high between data transfers and therefore the POL input of the AD7730 should be hardwired to a logic high. The 8XC51 outputs the ...
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AD7730/AD7730L APPLICATIONS The on-chip PGA allows the AD7730 to handle analog input voltage ranges as low full scale. This allows the user to connect a transducer directly to the input of the AD7730. The AD7730 is primarily ...
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Long lead lengths from the bridge to the AD7730 facilitate the pickup of mains frequency on the analog input, the reference input and the power supply. The analog inputs to the AD7730 are buffered, which allows the user to connect ...
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AD7730/AD7730L Bipolar Excitation of the Bridge As mentioned previously, some applications will require that the AD7730 handle inputs from a bridge that is excited by a bipolar voltage. The number of applications requiring this are limited, but with the addition ...
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APPENDIX A AD7730L SPECIFICATIONS –43– ...
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LOW POWER BRIDGE TRANSDUCER ADC KEY FEATURES Resolution of 110,000 Counts (Peak-to-Peak) Power Consumption typ Offset Drift: < 1 ppm/ C Gain Drift: 3 ppm/ C Line Frequency Rejection: >150 dB Buffered Differential Inputs Programmable Filter Cutoffs ...
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AD7730L–SPECIFICATIONS AV ; REF IN(–) = AGND = DGND = CLK IN Parameter STATIC PERFORMANCE (CHP = Missing Codes 2 Output Noise and Update Rates Integral Nonlinearity 2 Offset Error 2 Offset Drift ...
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AD7730/AD7730L Parameter LOGIC INPUTS Input Current All Inputs Except SCLK and MCLK Input Low Voltage INL V , Input Low Voltage INL V , Input High Voltage INH SCLK Only (Schmitt Trigerred Input ...
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NOTES 11 Temperature range: – + Sample tested during initial release. 13 The offset (or zero) numbers with CHP = 1 are typically 3 V precalibration. Internal zero-scale calibration reduces this by about 1 V. Offset ...
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AD7730/AD7730L OUTPUT NOISE AND RESOLUTION SPECIFICATION The AD7730L can be programmed to operate in either chop mode or nonchop mode. The chop mode can be enabled in ac-excited or dc-excited applications optional in dc-excited applications, but chop mode ...
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Table XXIII. Output Noise vs. Input Range and Update Rate (CHP = 0) Output – Settling Time Data Rate Frequency Word Normal Mode 75 Hz 2.9 Hz 2048 332 ms 100 Hz 3.9 Hz 1536 250 ms 150 ...
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AD7730/AD7730L PAGE INDEX Topic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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MAX 0.200 (5.05) 0.125 (3.18) 0.0118 (0.30) 0.0040 (0.10) 0.006 (0.15) 0.002 (0.05) SEATING PLANE REV. A OUTLINE DIMENSIONS Dimensions shown in inches and (mm). Plastic DIP (N-24) 1.275 (32.30) 1.125 (28.60 0.280 (7.11) 0.240 (6.10) ...
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