AD7701ARS Analog Devices Inc, AD7701ARS Datasheet
AD7701ARS
Specifications of AD7701ARS
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AD7701ARS Summary of contents
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FEATURES Monolithic 16-Bit ADC 0.0015% Linearity Error On-Chip Self-Calibration Circuitry Programmable Low-Pass Filter 0 Corner Frequency +2 2.5 V Analog Input Range 4 kSPS Output Data Rate Flexible Serial Interface Ultralow ...
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AD7701–SPECIFICATIONS Bipolar Mode: MODE = + Source Resistance = 1k IN Parameter A, S Version STATIC PERFORMANCE Resolution 16 Integral Nonlinearity MIN MAX ± 0.003 Differential Nonlinearity ± 0.125 MIN MAX ± ...
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Parameter A, S Version 8 POWER REQUIREMENTS Power Supply Voltages Analog Positive Supply (AV ) 4.5/5.5 DD Digital Positive Supply (DV ) 4.5/AV DD Analog Negative Supply (AV ) –4.5/–5.5 SS Digital Negative Supply (DV ) –4.5/–5.5 SS Calibration Memory ...
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... SS AGND to DGND . . . . . . . . . . . . . . . . . . . . . –0 +0.3 V Digital Input Voltage to DGND . . . . –0 Analog Input Voltage to AGND . . . . . . . . AV SS Input Current to Any Pin Except Supplies Model AD7701AN AD7701BN AD7701AR AD7701BR AD7701ARS AD7701AQ AD7701BQ AD7701SQ AD7701TQ *N = PDIP CERDIP SOIC SSOP. PDIP, CERDIP, SOIC MODE 1 CLKOUT 2 3 CLKIN ...
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Pin No. PDIP, CERDIP, SOIC SSOP Mnemonic Description 1 1 MODE 2 2 CLKOUT 3 3 CLKIN SC1, SC2 5 5 DGND 11, NC 18, 21, 22 ...
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AD7701 TIMING CHARACTERISTICS Limit MIN MAX Parameter (A, B Versions 200 CLKIN 5 200 1000 3 ...
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I OL 1.6mA TO + 2.1V OUTPUT C PIN L 100pF I OH 200µA Figure 1. Load Circuit for Access Time and Bus Relinquish Time HI-Z DATA SDATA VALID Figure 3. SSC Mode Data Hold Time CLKIN ...
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AD7701 Offset Calibration Range In the system calibration modes (SC2 low), the AD7701 cali- brates its offset with respect to the A pin. The offset calibration IN range specification defines the range of voltages, expressed as a percentage of V ...
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C CLOCK INTEGRATOR STROBED COMPARATOR R +V REF –V REF 1-BIT DAC Figure 9. SEC Basic Charge-Balancing ADC The term charge-balancing comes from the fact that this system is a negative feedback loop that tries to keep ...
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AD7701 The output settling of the AD7701 in response to a step input change is shown in Figure 12. The Gaussian response has fast settling with no overshoot, and the worst-case settling time to ± 0.0007% (± 0.5 LSB) is ...
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INPUT SIGNAL CONDITIONING Reference voltages from may be used with the AD7701 with little degradation in performance. Input ranges that cannot be accommodated by this range of reference voltages may be achieved by input signal ...
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AD7701 VOLTAGE REFERENCE CONNECTIONS The voltage applied to the V pin defines the analog input REF range. The specified reference voltage is 2.5 V, but the AD7701 will operate with reference voltages from with little ...
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CAL SC1 SC2 Calibration Type 0 0 Self-Calibration 1 1 System Offset 0 1 System Gain 1 0 System Offset *DRDY remains high throughout the calibration sequence. In the Self-Calibration mode, DRDY falls once the AD7701 has settled to the ...
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AD7701 0.1µF 10k REF 10V 1V AD707 10k 0.1µF Figure 17. Single-Supply Operation SLEEP MODE The low power standby mode is initiated by taking the SLEEP input low, which shuts down all analog and digital circuits and reduces power consumption ...
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Synchronous External Clock Mode (SEC) The SEC mode (MODE pin grounded) is designed for direct interface to the synchronous serial ports of industry-standard microprocessors such as the COPS series, 68HC11, and 68HC05. The SEC mode also allows customized interfaces, using ...
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AD7701 Asynchronous Communications (AC) Mode The AC mode (MODE pin tied to –5 V) offers a UART com- patible interface that allows the AD7701 to transmit data asynchronously from remote locations. An external SCLK sets the baud rate and data ...
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Plastic Dual In-Line Package [PDIP] (N-20) Dimensions shown in inches and (millimeters) 0.985 (25.02) 0.965 (24.51) 0.945 (24.00 0.180 (4.57) 0.015 (0.38) MIN MAX 0.150 (3.81) 0.130 (3.30) SEATING 0.100 0.060 (1.52) 0.110 (2.79) 0.022 ...
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AD7701 Revision History Location 3/03—Data Sheet changed from REV REV. E. Updated Format . . . . . . . . . . . . . . . . . . . . . . . . . ...
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