AD7710ARZ Analog Devices Inc, AD7710ARZ Datasheet - Page 21

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AD7710ARZ

Manufacturer Part Number
AD7710ARZ
Description
IC ADC 24BIT DIFF INP 24-SOIC
Manufacturer
Analog Devices Inc
Datasheet

Specifications of AD7710ARZ

Data Interface
Serial
Number Of Bits
24
Sampling Rate (per Second)
1.03k
Number Of Converters
1
Power Dissipation (max)
45mW
Voltage Supply Source
Analog and Digital, Dual ±
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
24-SOIC (0.300", 7.50mm Width)
Resolution (bits)
24bit
Input Channel Type
Differential
Supply Voltage Range - Digital
4.75V To 5.25V
Supply Current
4.5mA
Digital Ic Case Style
SOIC
No. Of Pins
24
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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REV. G
Write Operation
Data can be written to either the control register or calibration
registers. In either case, the write operation is not affected by
the DRDY line and does not have any effect on the status of
DRDY. A write operation to the control registers or calibration
register must always write 24 bits.
Figure 11 shows a write operation to the AD7710. A0 determines
whether a write operation transfers data to the control register or to
the calibration registers. This A0 signal must remain valid for the
duration of the serial write operation. The falling edge of TFS
enables the internally generated SCLK output. The serial data
to be loaded to the AD7710 must be valid on the rising edge of
this SCLK signal. Data is clocked into the AD7710 on the rising
edge of the SCLK signal with the MSB transferred first. On the
last active high time of SCLK, the LSB is loaded to the AD7710.
Subsequent to the next falling edge of SCLK, the SCLK output is
turned off. (The timing diagram in Figure 11 assumes a pull-up
resistor on the SCLK line.)
External Clocking Mode
The AD7710 is configured for external clocking mode by
tying the MODE pin low. In this mode, SCLK of the AD7710
is configured as an input, and an external serial clock must be
provided to this SCLK pin. This external clocking mode is
designed for direct interface to systems that provide a serial
clock output that is synchronized to the serial data output,
including microcontrollers such as the 80C51, 87C51, 68HC11,
68HC05, and most digital signal processors.
SDATA (I)
SCLK (O)
TFS (I)
A0 (I)
Figure 11. Self-Clocking Mode, Control/Calibration Register Write Operation
t
14
t
16
t
18
MSB
–21–
Read Operation
As with self-clocking mode, data can be read from either the
output register, the control register, or the calibration registers.
A0 determines whether the data read accesses data from the
control register or from the output/calibration registers. This A0
signal must remain valid for the duration of the serial read
operation. With A0 high, data is accessed from either the output
register or from the calibration registers. With A0 low, data is
accessed from the control register.
The function of the DRDY line is dependent only on the output
update rate of the device and the reading of the output data
register. DRDY goes low when a new data-word is available in
the output data register. It is reset high when the last bit of data
(either 16th bit or 24th bit) is read from the output register. If
data is not read from the output register, the DRDY line will
remain low. The output register will continue to be updated at
the output update rate, but DRDY will not indicate this. A read
from the device in this circumstance will access the most recent
word in the output register. If a new data-word becomes avail-
able to the output register while data is being read from the
output register, DRDY will not indicate this and the new data-
word will be lost to the user. DRDY is not affected by reading
from the control register or the calibration register.
Data can be accessed from the output data register only when
DRDY is low. If RFS goes low while DRDY is high, no data
transfer will take place. DRDY does not have any effect on reading
data from the control register or from the calibration registers.
t
19
t
9
t
10
LSB
t
17
t
15
AD7710

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