AD9649BCPZ-65 Analog Devices Inc, AD9649BCPZ-65 Datasheet - Page 7

• Manufacturer Part Number: AD9649BCPZ-65
• Description: IC ADC 14BIT 65MSPS 32LFCSP
• Manufacturer: Analog Devices Inc

Specifications of AD9649BCPZ-65

• Data Interface: Serial, SPI™
• Number Of Bits: 14
• Sampling Rate (per Second): 65M
• Number Of Converters: 1
• Power Dissipation (max): 87.5mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-VFQFN, CSP Exposed Pad
• Resolution (bits): 14bit
• Sampling Rate: 65MSPS
• Input Channel Type: Differential
• Supply Voltage Range - Analog: 1.7V To 1.9V
• Supply Voltage Range - Digital: 1.7V To 3.6V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SWITCHING SPECIFICATIONS
AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty
cycle clock, unless otherwise noted.
Table 4.
Parameter
CLOCK INPUT PARAMETERS
DATA OUTPUT PARAMETERS
OUT-OF-RANGE RECOVERY TIME
1
2
Conversion rate is the clock rate after the CLK divider.
Wake-up time is dependent on the value of the decoupling capacitors.
Input Clock Rate
Conversion Rate
CLK Period, Divide-by-1 Mode (t
CLK Pulse Width High (t
Aperture Delay (t
Aperture Uncertainty (Jitter, t
Data Propagation Delay (t
DCO Propagation Delay (t
DCO to Data Skew (t
Pipeline Delay (Latency)
Wake-Up Time
Standby
2
1
A
)
CLK+
CLK–
DATA
DCO
SKEW
VIN
CH
)
)
PD
DCO
)
)
J
)
CLK
)
N – 1
t
CH
Temp
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
t
Min
50/25
PD
3
N
AD9649-20/AD9649-40
Figure 2. CMOS Output Data Timing
t
t
A
CLK
t
DCO
t
SKEW
N – 8
Typ
25.0/12.5
1.0
0.1
3
3
0.1
8
350
600/400
2
Rev. 0 | Page 7 of 32
N + 1
N – 7
Max
80/160
20/40
N + 2
N – 6
Min
3
15.38
N + 3
AD9649-65
Typ
7.69
1.0
0.1
3
3
0.1
8
350
300
2
N – 5
N + 4
Max
260
65
Min
3
12.5
N – 4
N + 5
AD9649-80
Typ
6.25
1.0
0.1
3
3
0.1
8
350
260
2
Max
320
80
AD9649
Unit
MHz
MSPS
ns
ns
ns
ps rms
ns
ns
ns
Cycles
μs
ns
Cycles