AD1877JR Analog Devices Inc, AD1877JR Datasheet - Page 3

IC ADC STEREO 16BIT 28-SOIC

AD1877JR

Manufacturer Part Number
AD1877JR
Description
IC ADC STEREO 16BIT 28-SOIC
Manufacturer
Analog Devices Inc
Datasheet

Specifications of AD1877JR

Rohs Status
RoHS non-compliant
Number Of Bits
16
Sampling Rate (per Second)
48k
Data Interface
Serial
Number Of Converters
2
Power Dissipation (max)
315mW
Voltage Supply Source
Analog and Digital
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
28-SOIC (0.300", 7.50mm Width)

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AD1877JR
Manufacturer:
ADI/亚德诺
Quantity:
20 000
Part Number:
AD1877JRZ
Manufacturer:
ADI/亚德诺
Quantity:
20 000
REV. A
DIGITAL I/O
Input Voltage HI (V
Input Voltage LO (V
Input Leakage (I
Input Leakage (I
Output Voltage HI (V
Output Voltage LO (V
Input Capacitance
DIGITAL TIMING (Guaranteed over 0°C to 70°C, DV
t
F
t
t
t
t
t
t
t
t
t
t
t
t
t
t
POWER
Supplies
Dissipation
CLKIN
CPWL
CPWH
RPWL
BPWL
BPWH
DLYCKB
DLYBLR
DLYBWR
DLYBWF
DLYDT
SETLRBS
DLYLRDT
SETWBS
DLYBDT
CLKIN
Voltage, Analog and Digital
Analog Current
Analog Current—Power Down (CLKIN Running)
Digital Current
Digital Current—Power Down (CLKIN Running)
Operation—Both Supplies
Operation—Analog Supply
Operation—Digital Supply
Power Down—Both Supplies (CLKIN Running)
Power Down—Both Supplies (CLKIN Not Running)
Power Supply Rejection (See TPC 5)
1 kHz 300 mV p-p Signal at Analog Supply Pins
20 kHz 300 mV p-p Signal at Analog Supply Pins
Stopband (≥0.55 × F
IH
IL
CLKIN Period
CLKIN Frequency (1/t
CLKIN LO Pulsewidth
CLKIN HI Pulsewidth
RESET LO Pulsewidth
BCLK LO Pulsewidth
BCLK HI Pulsewidth
CLKIN Rise to BCLK Xmit (Master Mode)
BCLK Xmit to LRCK Transition (Master Mode)
BCLK Xmit to WCLK Rise
BCLK Xmit to WCLK Fall
BCLK Xmit to Data/Tag Valid (Master Mode)
LRCK Setup to BCLK Sample (Slave Mode)
LRCK Transition to Data/TAG Valid (Slave Mode)
No MSB Delay Mode (for MSB Only)
WCLK Setup to BCLK Sample (Slave Mode)
Data Position Controlled by WCLK Input Mode
BCLK Xmit to DATA/TAG Valid (Slave Mode)
All Bits Except MSB in No MSB Delay Mode
All Bits in MSB Delay Mode
@ V
@ V
IH
IL
OH
)
)
OL
IL
IH
@ I
S
= 0 V)
@ I
= 5 V)
)—any 300 mV p-p Signal
OH
OL
= –2 mA)
= 2 mA)
CLKIN
)
DD
= AV
DD
–3–
= 5 V ± 5%. Refer to Figures 17–19.)
Min
2.4
2.4
Min
4.75
Min
48
1.28
15
15
50
15
15
10
10
Typ
Typ
5
35
6
16
13
255
175
80
95
5
76
71
80
Typ
81
12.288
Max
43
5.25
26
20
39
315
215
100
325
Max
0.8
10
10
0.4
15
Max
780
20.48
15
15
10
10
10
40
10
AD1877
Unit
V
V
µA
µA
V
V
pF
Unit
ns
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Unit
V
mA
µA
mA
µA
mW
mW
mW
µW
µW
dB
dB
dB

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