AD1871YRS-REEL Analog Devices Inc, AD1871YRS-REEL Datasheet - Page 18

• Manufacturer Part Number: AD1871YRS-REEL
• Description: IC ADC STEREO 24BIT 96KHZ 28SSOP
• Manufacturer: Analog Devices Inc

Specifications of AD1871YRS-REEL

• Rohs Status: RoHS non-compliant
• Number Of Bits: 24
• Sampling Rate (per Second): 96k
• Data Interface: Serial, SPI™
• Number Of Converters: 2
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 28-SSOP (0.200", 5.30mm Width)

AD1871
I
In I
placed in the second BCLK period following the transition of
the LRCLK. A high-to-low transition of the LRCLK signifies
LJ Mode
In LJ Mode, the data is left-justified, MSB first, with the MSB
placed in the first BCLK period following the transition of the
LRCLK. A high-to-low transition of the LRCLK signifies the
RJ Mode
In RJ Mode, the data is right-justified, LSB last, with the
LSB placed in the last BCLK period preceding the transition
of the LRCLK. A high-to-low transition of the LRCLK signifies
DSP Mode
In DSP Mode, the LRCLK signal becomes a frame sync signal
that pulses high for the BCLK period prior to the MSB (or in
the BCLK period of the previous LSB–32 bits). The data is left-
justified, MSB first, with the MSB placed in the BCLK period
following the LRCLK pulse (see Figure 15).
2
S Mode
LRCLK
LRCLK
LRCLK
LRCLK
DOUT
BCLK
DOUT
BCLK
DOUT
BCLK
2
DOUT
BCLK
S Mode, the data is left-justified, MSB first, with the MSB
LSB
MSB
MSB
MSB– 1
MSB
MSB– 1
MSB– 2
MSB–1
MSB– 2
LEFT CHANNEL
MSB
LSB+2
LEFT CHANNEL
LSB+2 LSB+1
LEFT CHANNEL
MSB–1
LEFT CHANNEL
LSB+2 LSB+1
LSB+1
MSB–2
LSB
LSB
LSB
Figure 14. Right-Justified Mode
Figure 13. Left-Justified Mode
Figure 15. DSP Mode
Figure 12. I
LSB+2 LSB+1
–18–
LSB
MSB
2
S Mode
the beginning of the left channel data transfer, while a low-to-
high transition on the LRCLK signifies the beginning of the
right channel data transfer (see Figure 12).
beginning of the right channel data transfer, while a low-to-high
transition on the LRCLK signifies the beginning of the left
channel data transfer (see Figure 13).
the beginning of the right channel data transfer, while a low-to-
high transition on the LRCLK signifies the beginning of the left
channel data transfer (see Figure 14).
In I
data word-width between the AD1871 and the controller are not
catastrophic since the MSBs are guaranteed to be transferred.
There may, however, be a slight reduction in performance
depending on the scale of the mismatch. In RJ Mode, however,
differences in word-width between the AD1871 and controller
have a catastrophic effect on signal performance as the MSBs
of each sample may be lost due to the mismatch.
MSB
MSB– 1
2
MSB
S and LJ Modes, since the data is left-justified, differences in
MSB– 1
MSB– 2
MSB–1
MSB– 2
RIGHT CHANNEL
RIGHT CHANNEL
RIGHT CHANNEL
MSB
LSB+2
LSB+2 LSB+1
RIGHT CHANNEL
LSB+2 LSB+1
MSB–1
LSB+1
MSB–2
LSB
LSB
LSB
LSB+2 LSB+1
LSB
MSB
MSB
MSB
MSB–1
MSB– 1
REV. 0