AD1871 Analog Devices, AD1871 Datasheet
AD1871
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AD1871 Summary of contents
Page 1
... Analog Devices. 96 kHz, Multi-bit Σ∆ ADC PRODUCT OVERVIEW The AD1871 is a stereo audio ADC intended for digital audio applications requiring high performance analog-to-digital conversion. It features two 24-bit conversion channels each with programmable gain amplifier (PGA), multi-bit sigma-delta modulator and decimation filters ...
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... PRELIMINARY TECHNICAL DATA AD1871–SPECIFICATIONS TEST CONDITIONS UNLESS OTHERWISE NOTED Supply Voltages Ambient Temperature ) [256 ∞ F Input Clock (F ] CLKIN S Input Signal Measurement Bandwidth Word Width Load Capacitance on Digital Outputs 100 Input Voltage Input Voltage Master Mode, Data I2S-Justified. ANALOG PERFORMANCE ...
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... HIGH PASS DIGITAL FILTER CHARACTERISTICS Passband Frequency Stopband Frequency Passband Ripple Stopband Attenuation Group Delay REV. PrD 02/2002 Min Typ 128 ±0.0001 120 TBD Min Typ TBD TBD – 3 – AD1871 Max Units kHz kHz dB dB µs Max Units Hz TBD Hz TBD dB dB TBD s ...
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... PRELIMINARY TECHNICAL DATA AD1871 DATA INTERFACE TIMING Mnemonic Description t BCLK High Width DBH t BCLK Low Width DBL t BCLK Period DBP t Delay from LRCLK transition to BCLK high DLS t BCLK High Period DDS t BCLK High Period DDH t DBH BCLK t DBL t DLS LRCLK t DDS ...
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... Specifications subject to change without notice. REV. PrD 02/2002 Min Typ 2.4 ODVDD-0.4V Min Typ 4.5 5 2.7 34 TBD 16 0.5 TBD TBD TBD TBD TBD Min Typ 25 -40 –65 – 5 – AD1871 Max Unit V 0 µA 10 µ Max Unit 5 µ µA µ ...
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... ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD1871 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality ...
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... Right Channel Positive Input (via MUX/PGA) Right Channel Negative Input (via MUX/PGA) Analog Ground Cascade Enable - This pin enables cascading AD1871 devices to a single DSP serial port. (See Cascading section) Digital Ground Digital Interface Supply - The digital interface can operate from 3.3V to 5.0V (nominal) ...
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... DSP - Digital Signal Processor IMCLK - Internal master clock signal, used to clock the decimating filter section (its frequency must be 256*fs). MCLK - External master clock signal applied to the AD1871. Its frequency can be 256, 512 or 768 *fs. MCLK is divided internally to give an IMCLK frequency which must be 256*fs. ...
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... MCLK Figure <Clock_Scheme.eps> Clocking Scheme to Modulator and Filter Engine Modulator The AD1871's analog Σ∆ modulator section comprises a second-order multi-bit implementation using Analog Device's proprietary technology for best performance. As shown in Figure <Mod_FBD.eps>, the two analog integrator blocks are followed by a flash ADC section which generates the multi-bit samples ...
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... Sinc and FIR filter sections. TPC 5 gives the composite response of the sinc and FIR filters. High Pass Filter The AD1871 features an optional high-pass filter section which provides the ability of rejecting DC from the output datastream. The high-pass filter is enabled by setting bit 8 (HPE) of Control Register I to " ...
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... Left and Right Channel samples and its frequency is equal to the sampling frequency (fs). BCLK is the serial clock used to clock the data samples from the AD1871 and its frequency is equal to 64*fs (giving 32 BCLK periods for each of the Left and Right Channels). SDATA outputs the Left and Right Channel sample data coincident with the rising/falling edge of BCLK ...
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... MSB first, with the MSB placed in the BCLK period following the LRCLK.pulse (see Figure <DSP_Mode.eps>). and LJ modes, as the data is left-justified, differences in data word-width between the AD1871 and the controller are LRCLK LEFT BCLK DOU ...
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... AD1871 devices. The DSP can be master and supply the frame sync and serial clock to the AD1871s or one of the AD1871s can be set as master with the DSP and all other AD1871s set to slave. Each sampling period begins with a frame sync being generated; ...
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... AD1871's Control Port. Table <Control/Status Word Format> details the format of the AD1871 control words, which are 16-bits wide with a 4-bit address field in positions 15 through 12, a Read/Write bit in position 11, a reserved bit in position 10 and ten bits of register data (corresponding to the control register width) in positions 9 through 0 ...
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... MCLK frequency. Please refer to the Functional Description section for more information on MCLK selection and sampling rates. Powerdown Powerdown of the active clock signals within the AD1871 is effected by writing a logical 1 to bit 7 (PD). High Pass Filter The AD1871's digital filtering engine allows the insertion of a high pass filter (HPF) to effectively block DC signals from the output digital waveform ...
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... Master/Slave Select The AD1871 can operate as either a slave device or a master device. In slave mode, the controller must provide the LRCLK and BCLK to determine the sample rate and serial bit rate. In master mode, the AD1871 provides the LRCLK and BCLK as outputs which are applied to the controller ...
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... MCLK is not at 256*fs, but is a multiple of this, the MCD allows conversion of MCLK to a suitable IMCLK at 256*fs. (See Table <Master Clock Divider Settings>.) Table <Master Clock Divider Settings> Master Clock * MCD1 MCD0 –17– AD1871 MXR Input SER ...
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... PRELIMINARY TECHNICAL DATA AD1871 Table <Peak_Rdg_I> Peak Reading Register I (Address 0011b - Read Only) 15- 0011 9-6 5-0 Table <Peak_Rdg_II> Peak Reading Register II (Address 0100b - Read Only) 15- 0100 9-6 5-0 Peak Reading Registers The Peak Reading Registers are read-only registers which can be enabled to track and hold the peak ADC reading from each channel ...
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... The Master/Slave hardware select (pin 27 - CIN/(M/S))is equivalent to setting the M/S bit of Control Register II. If set low, the device is placed in master mode, whereby the LRCLK and BCLK signals are outputs from the AD1871. When M/S is set high, the device is in slave mode, whereby the LRCK and BCLK signals must be provided as inputs to the AD1871 ...
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... PRELIMINARY TECHNICAL DATA AD1871 TYPICAL PERFORMANCE CURVES Filter Responses 0 −20 −40 −60 −80 −100 −120 −140 −160 0 5 Frequency − Normalised to fs TPC <Sinc_AMC_0.eps> Sinc Filter Response (AMC = 0) 0 −20 −40 −60 −80 −100 −120 −140 −160 0 5 Frequency − Normalised to fs TPC < ...
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... TPC <HPF96.eps> High Pass Filter Response - f REV. PrD 02/2002 Device Performance Curves = 48 kHz S TPC <> 1 kHz Tone at -0.5 dBFS, (32k-point FFT kHz S TPC <> 1 kHz Tone at -20 dBFS, (32k-point FFT TPC <> 1 kHz Tone at -60 dBFS, (32k-point FFT –21– AD1871 kHz kHz kHz ...
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... PRELIMINARY TECHNICAL DATA AD1871 TPC <> THD+N versus Input Amplitude at 1 kHz kHz TPC <> THD+N versus Input Frequency at -0.5 dBFS kHz TPC <> Channel Seperation versus Frequency at -0.5 dBFS kHz –22– REV. PrD 02/2002 ...
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... PGA section of the AD1871. The PGA section is configured for Single-Ended to Differential conversion. The differential outputs are connected internally to the CAPxx pins via 250Ω series resistors. In order to configure the AD1871 for single-ended input , the control registers must be configured as follows: Left Channel: Control Register I = xx0xGGGxxx where GGG = Input Gain (see Table < ...
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... PGA section is configured as a differential buffer. The buffered differential outputs are connected internally to the CAPxx pins via 250Ω series resistors. In order to configure the AD1871 for differential input via the Mux/PGA , the control registers must be configured as follows: Left Channel: Control Register I = xx0xGGGxxx where GGG = Input Gain (see Table < ...
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... However, because the resolution of the AD1871’s ADC is high, and the noise levels from the AD1871 are so low, care must be taken with regard to grounding and layout. The printed circuit board that houses the AD1871 should be designed so the analog and digital sections are separated and confined to certain sections of the board ...
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... PRELIMINARY TECHNICAL DATA AD1871 Contents AD1871–SPECIFICA- TIONS 2 –26– REV. PrD 02/2002 ...
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... REV. PrD 02/2002 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 28-Lead Shrink Small Outline IC (RS-28) 0.407 (10.34) 0.397 (10.08 0.07 (1.79) PIN 1 0.066 (1.67) 8¡ 0.0256 0.015 (0.38) 0¡ SEATING 0.009 (0.229) (0.65) 0.010 (0.25) PLANE BSC 0.005 (0.127) –27– AD1871 0.03 (0.762) 0.022 (0.558) ...