AD7921ARM Analog Devices Inc, AD7921ARM Datasheet - Page 8

• Manufacturer Part Number: AD7921ARM
• Description: IC ADC 12BIT DUAL LP 8-MSOP
• Manufacturer: Analog Devices Inc

Specifications of AD7921ARM

• Number Of Bits: 12
• Sampling Rate (per Second): 250k
• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Converters: 1
• Power Dissipation (max): 20mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-TSSOP, 8-MSOP (0.118", 3.00mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

AD7911/AD7921
TIMING EXAMPLES
Figure 6 and Figure 7 show some of the timing parameters from
the Timing Specifications section.
Timing Example 1
As shown in Figure 7, when f
250 kSPS, the cycle time is
With t
the requirement of 290 ns for t
In Figure 7, t
t
satisfying the minimum requirement of 30 ns.
10
= 30 ns maximum. This allows a value of 960 ns for t
t
2
2
+ 12.5(1/f
= 10 ns minimum, then t
ACQ
SCLK
DOUT
SCLK
is comprised of 2.5(1/f
SCLK
DIN
CS
CS
) + t
THREE-STATE
ACQ
t
t
= 4 µs
2
2
X
Z
SCLK
1
1
ACQ
t
ZERO
3
ACQ
= 5 MHz and the throughput is
.
X
is 1.49 µs, which satisfies
2
2
CHN
SCLK
t
CHN
8
) + t
3
3
10
12.5(1/f
X
+ t
Figure 6. AD7921 Serial Interface Timing Diagram
X
t
4
4
9
QUIET
SCLK
Figure 7. Serial Interface Timing Example
DB11
t
t
6
4
, where
QUIET
)
t
t
X
CONVERT
CONVERT
5
5
t
DB10
7
,
Rev. 0 | Page 8 of 28
1/THROUGHPUT
X
13
13
B
Timing Example 2
The AD7921 can also operate with slower clock frequencies. As
shown in Figure 7, when f
is 100 KSPS, the cycle time is
With t
the requirement of 290 ns for t
In Figure 7, t
t
satisfying the minimum requirement of 30 ns.
In this example, as with other slower clock values, the signal
might already be acquired before the conversion is complete,
but it is still necessary to leave 30 ns minimum t
conversions. In this example, the signal should be fully acquired
at approximately point C in Figure 7.
10
DB2
B
= 30 ns maximum. This allows a value of 2.46 µs for t
X
14
t
14
2
t
5
2
+ 12.5(1/f
C
= 10 ns minimum, then t
DB1
X
15
t
15
10
ACQ
DB0
is comprised of 2.5(1/f
SCLK
t
ACQUISITION
X
16
16
) + t
THREE-STATE
t
ACQ
10
SCLK
= 10 µs
= 2 MHz and the throughput rate
t
QUIET
t
ACQ
QUIET
ACQ
.
t
1
is 3.74 µs, which satisfies
SCLK
) + t
10
QUIET
+ t
QUIET
between
, where
QUIET
,