AD9219BCPZ-40 Analog Devices Inc, AD9219BCPZ-40 Datasheet - Page 35
![IC ADC 10BIT QUAD 40MSPS 48LFCSP](/photos/6/50/65022/cp-48-8_sml.jpg)
AD9219BCPZ-40
Manufacturer Part Number
AD9219BCPZ-40
Description
IC ADC 10BIT QUAD 40MSPS 48LFCSP
Manufacturer
Analog Devices Inc
Datasheet
1.AD9219ABCPZRL7-40.pdf
(52 pages)
Specifications of AD9219BCPZ-40
Data Interface
Serial, SPI™
Number Of Bits
10
Sampling Rate (per Second)
40M
Number Of Converters
4
Power Dissipation (max)
313mW
Voltage Supply Source
Analog and Digital
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
48-VFQFN, CSP Exposed Pad
Resolution (bits)
10bit
Sampling Rate
40MSPS
Input Channel Type
Differential
Supply Voltage Range - Analog
1.7V To 1.9V
Supply Voltage Range - Digital
1.7V To 1.9V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AD9219-65EBZ - BOARD EVALUATION FOR AD9219AD9219-65EB - BOARD EVALUATION FOR AD9219
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Power and Ground Recommendations
When connecting power to the AD9219, it is recommended
that two separate 1.8 V supplies be used: one for analog (AVDD)
and one for digital (DRVDD). If only one supply is available, it
should be routed to the AVDD first and then tapped off and
isolated with a ferrite bead or a filter choke preceded by
decoupling capacitors for the DRVDD. The user can employ
several different decoupling capacitors to cover both high and
low frequencies. These should be located close to the point of
entry at the PC board level and close to the parts, with minimal
trace lengths.
A single PC board ground plane should be sufficient when
using the AD9219. With proper decoupling and smart parti-
tioning of the PC board’s analog, digital, and clock sections,
optimum performance can be easily achieved.
Rev. D | Page 35 of 52
Exposed Paddle Thermal Heat Slug Recommendations
It is required that the exposed paddle on the underside of the
ADC be connected to analog ground (AGND) to achieve the
best electrical and thermal performance of the AD9219. An
exposed continuous copper plane on the PCB should mate to
the AD9219 exposed paddle, Pin 0. The copper plane should
have several vias to achieve the lowest possible resistive thermal
path for heat dissipation to flow through the bottom of the PCB.
These vias should be solder-filled or plugged.
To maximize the coverage and adhesion between the ADC and
PCB, partition the continuous copper plane by overlaying a
silkscreen on the PCB into several uniform sections. This provides
several tie points between the ADC and PCB during the reflow
process, whereas using one continuous plane with no partitions
only guarantees one tie point. See Figure 70 for a PCB layout
example. For detailed information on packaging and the PCB
layout of chip scale packages, see the AN-772 Application Note,
A Design and Manufacturing Guide for the Lead Frame Chip
Scale Package (LFCSP), at www.analog.com.
SILKSCREEN PARTITION
PIN 1 INDICATOR
Figure 70. Typical PCB Layout
AD9219