LTC1093CSW Linear Technology, LTC1093CSW Datasheet - Page 23

• Manufacturer Part Number: LTC1093CSW
• Description: IC DATA ACQ SYS 10BIT 6CH 16SOIC
• Manufacturer: Linear Technology
• Type: Data Acquisition System (DAS), ADCr

Specifications of LTC1093CSW

• Resolution (bits): 10 b
• Data Interface: Serial
• Voltage Supply Source: Dual ±
• Voltage - Supply: 4.5 V ~ 10 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-SOIC (0.300", 7.5mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Sampling Rate (per Second): -

A
RC Input Filtering
It is possible to filter the inputs with an RC network as
shown in Figure 11. For large values of C
capacitive input switching currents are averaged into a net
DC current. Therefore, a filter should be chosen with a small
resistor and large capacitor to prevent DC drops across the
resistor. The magnitude of the DC current is approximately
I
When running at the minimum cycle time of 32 s, the input
current equals 9 A at V
of 50 will cause 0.1LSB of full-scale error. If a larger filter
DC
Figure 9. Adequate Settling of Op Amp Driving Analog Input
PPLICATI
= (60pF)(V
5mV/DIV
Figure 10. Poor Op Amp Settling Can Cause A/D Errors
5mV/DIV
IN
/t
O
CYC
U
) and is roughly proportional to V
S
IN
= 5V. In this case, a filter resistor
20 s/DIV
1 s/DIV
I FOR ATIO
U
W
F
1091-4 F09
1091-4 F10
(e.g., 1 F), the
U
IN
.
resistor must be used, errors can be eliminated by increas-
ing the cycle time as shown in the typical curve of Maximum
Filter Resistor vs Cycle Time.
Input Leakage Current
Input leakage currents can also create errors if the source
resistance gets too large. For instance, the maximum input
leakage specification of 1 A (at 125 C) flowing through a
source resistance of 1k will cause a voltage drop of 1mV
or 0.2LSB. This error will be much reduced at lower
temperatures because leakage drops rapidly (see the
typical curve of Input Channel Leakage Current vs
Temperature).
4. Sample-and-Hold
Single-Ended Inputs
The LTC1091/LTC1093/LTC1094 provide a built-in sample-
and-hold (S&H) function for all signals acquired in the single-
ended mode. This sample-and-hold allows conversion of
rapidly varying signals (see typical curve of S&H Acquisition
Time vs Source Resistance). The input voltage is sampled
during the t
interval begins as the bit preceding the MSBF bit is shifted in
and continues until the falling CLK edge after the MSBF bit is
received. On this falling edge, the S&H goes into hold mode
and the conversion begins.
SMPL
V
IN
Figure 11. RC Input Filtering
R
time as shown in Figure 8. The sampling
FILTER
I
DC
LTC1093/LTC1094
LTC1091/LTC1092
C
FILTER
“+”
“–”
LTC1091
1091-4 F11
23