AD7879-1ACPZ-RL Analog Devices Inc, AD7879-1ACPZ-RL Datasheet - Page 29

• Manufacturer Part Number: AD7879-1ACPZ-RL
• Description: IC ADC 12BIT CTLR TOUCH 16LFCSP
• Manufacturer: Analog Devices Inc
• Type: Resistiver

Specifications of AD7879-1ACPZ-RL

• Resolution (bits): 12 b
• Data Interface: I²C, Serial
• Touch Panel Interface: 4-Wire
• Number Of Inputs/keys: 1 TSC
• Data Rate/sampling Rate (sps, Bps): 105k
• Voltage Reference: External
• Voltage - Supply: 1.6 V ~ 3.6 V
• Current - Supply: 10nA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-LFCSP
• Voltage Supply Source: Single Supply
• Sampling Rate (per Second): 105k
• Sampling Rate: 105kSPS
• Supply Voltage Range - Analog: 1.6V To 3.6V
• Supply Current: 480µA
• Digital Ic Case Style: CSP
• No. Of Pins: 16
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

CONTROL REGISTER 3
Control Register 3 (Address 0x03) includes the interrupt
register (Bits[15:8]) and the sequencer bits (Bits[7:0]).
Sequencer (Control Register 3, Bits[7:0])
The sequencer bits control which channels are converted during
a conversion sequence in both slave mode and master mode.
To include a measurement in a sequence, the relevant bit must
be set in the sequence. Setting Bit 7 includes a measurement on
the X+ channel (Y position). Setting Bit 6 includes a measure-
ment on the Y+ channel (X position), and so on (see Table 14).
Figure 32 illustrates the correspondence between the bits in
Control Register 3 and the various measurements. Bit 0 is
not used.
CONVERSION
SINGLE
01
Figure 33. Conversion Modes
WAIT FOR TIMER
CONVERSION
SLAVE MODE
START TIMER
ADC MODE?
TIMER = 00?
SEQUENCE
15
MASK
TEMP
IDLE
10
NO
MASK
VBAT
AUX/
00
MODE
INT
ALERT
GPIO
WAIT FOR TIMER
MASTER MODE
FIRST TOUCH
CONVERSION
START TIMER
TIMER = 00?
SEQUENCE
TOUCHED?
TOUCHED?
WAIT FOR
SCREEN
SCREEN
VBAT
AUX/
LOW
YES
NO
YES
11
VBAT
AUX/
HIGH
YES
NO
NO
Figure 32. Control Register 3
TEMP
LOW
Rev. C | Page 29 of 40
TEMP
HIGH
X+
Y+
Z1
NO
1
Z2
SET ALERT AND
MEDIAN # MEANS MEDIAN
AVERAGE DATA
FILTER SIZE.
# OF SAMPLES
(WAIT t
INTERRUPT
RANK NEW
CONVERSION
TAKEN?
MEDIAN
SEQUENCE
START OF
DATA
AUX
YES
Figure 34. Conversion Sequence
SORT
FCD
1
VBAT TEMP
)
YES
YES
YES
USED
TRANSFER DATA
CONVERT DATA
NOT
TO REGISTERS
SET CHANNEL
ACQUISITION
MAV FILTER
SEQUENCE
WAIT FOR
ENABLED
OUT-OF-
REQ’D?
END OF
LIMIT?
0
AD7879/AD7889
FCD
ACQ
FCD
?
?
NO
NO
NO
YES
NO