AD9277BSVZ Analog Devices Inc, AD9277BSVZ Datasheet
AD9277BSVZ
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AD9277BSVZ Summary of contents
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FEATURES 8 channels of LNA, VGA, AAF, ADC, and I/Q demodulator Low noise preamplifier (LNA) Input-referred noise: 0.75 nV/√Hz typical at 5 MHz (gain = 21.3 dB) SPI-programmable gain: 15.6 dB/17.9 dB/21.3 dB Single-ended input: V maximum = 733 mV ...
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AD9277 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 Product Highlights ........................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 General Description ......................................................................... 3 Specifications ..................................................................................... 4 AC Specifications .......................................................................... 4 Digital Specifications ................................................................... 7 Switching Specifications ...
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GENERAL DESCRIPTION The AD9277 is designed for low cost, low power, small size, and ease of use. It contains eight channels of a variable gain amplifier (VGA) with a low noise preamplifier (LNA); an anti- aliasing filter (AAF); a 14-bit, ...
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AD9277 SPECIFICATIONS AC SPECIFICATIONS AVDD1 = 1.8 V, AVDD2 = 3.0 V, DRVDD = 1.8 V, 1.0 V internal ADC reference, f PGA gain = 24 dB, GAIN− = 0.8 V, AAF LPF cutoff = f full temperature, ANSI-644 LVDS ...
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Parameter Noise Figure Active Termination Matched Unterminated Correlated Noise Ratio Output Offset Signal-to-Noise Ratio (SNR) Harmonic Distortion Second Harmonic Third Harmonic Two-Tone Intermodulation (IMD3) Channel-to-Channel Crosstalk Channel-to-Channel Delay Variation PGA Gain GAIN ACCURACY Gain Law Conformance Error Linear Gain ...
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AD9277 1 Parameter Noise Figure Input-Referred Dynamic Range Output-Referred SNR Two-Tone Intermodulation (IMD3) Quadrature Phase Error I/Q Amplitude Imbalance Channel-to-Channel Matching POWER SUPPLY AVDD1 AVDD2 DRVDD I AVDD1 I AVDD2 I DRVDD Total Power Dissipation (Including Output Drivers) Power-Down Dissipation ...
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DIGITAL SPECIFICATIONS AVDD1 = 1.8 V, AVDD2 = 3.0 V, DRVDD = 1.8 V, 1.0 V internal ADC reference, f Table 2. Parameter 1 CLOCK INPUTS (CLK+, CLK−) Logic Compliance 2 Differential Input Voltage Input Common-Mode Voltage Input Resistance (Differential) ...
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AD9277 SWITCHING SPECIFICATIONS AVDD1 = 1.8 V, AVDD2 = 3.0 V, DRVDD = 1.8 V, 1.0 V internal ADC reference, f Table 3. 1 Parameter 2 CLOCK Clock Rate Clock Pulse Width High ( Clock Pulse Width Low ...
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ADC TIMING DIAGRAMS N – 1 AIN t EH CLK– CLK+ t CPD DCO– DCO+ t FCO FCO– FCO DOUTx– DOUTx+ N – 1 AIN t EH CLK– CLK+ t CPD DCO– DCO+ t FCO FCO– FCO+ t ...
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AD9277 ABSOLUTE MAXIMUM RATINGS Table 4. Parameter AVDD1 to GND AVDD2 to GND DRVDD to GND GND to GND AVDD2 to AVDD1 AVDD1 to DRVDD AVDD2 to DRVDD Digital Outputs (DOUTx+, DOUTx−, DCO+, DCO−, FCO+, FCO−) to GND CLK+, CLK−, ...
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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS PIN 1 LI-E 1 INDICATOR LG-E 2 AVDD2 3 AVDD1 4 LO-F 5 LOSW-F 6 LI-F 7 LG-F 8 AVDD2 9 AVDD1 10 LO-G 11 LOSW-G 12 LI-G 13 LG-G 14 AVDD2 15 AVDD1 16 ...
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AD9277 Pin No. Name 23 CLK− 24 CLK+ 26, 47 DRVDD 27 DOUTH− 28 DOUTH+ 29 DOUTG− 30 DOUTG+ 31 DOUTF− 32 DOUTF+ 33 DOUTE− 34 DOUTE+ 35 DCO− 36 DCO+ 37 FCO− 38 FCO+ 39 DOUTD− 40 DOUTD+ 41 ...
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Pin No. Name 89 RBIAS 90 VREF 92 CWI− 93 CWI+ 94 CWQ− 95 CWQ+ 99 LO-E 100 LOSW-E Description External Resistor to Set the Internal ADC Core Bias Current. Voltage Reference Input/Output. CW Doppler I Output Complement. CW Doppler ...
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AD9277 TYPICAL PERFORMANCE CHARACTERISTICS TGC MODE MSPS MHz Ω, LNA gain = 21.3 dB, LNA bias = high, PGA gain = 24 dB, AAF LPF cutoff = f SAMPLE IN S ...
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CODES Figure 11. Output-Referred Noise Histogram, GAIN+ = 0.0 V 70,000 60,000 50,000 40,000 30,000 20,000 10,000 0 –35 –30 –25 –20 ...
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AD9277 0 –10 –20 –30 –40 GAIN+ = 0.4V –50 GAIN+ = 1.0V –60 –70 GAIN+ = 1.6V –80 – INPUT FREQUENCY (MHz) Figure 17. Second-Order Harmonic Distortion vs. Frequency, AIN = −1.0 dBFS 0 ...
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CW DOPPLER MODE f = 2.5 MHz at −3 dBFS MHz 4LO 1.2 1.0 0.8 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 –1.2 100 1k BASEBAND FREQUENCY (Hz) Figure 23. Quadrature Phase Error ...
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AD9277 170 168 166 LNA GAIN = 15.6dB 164 LNA GAIN = 17.9dB 162 LNA GAIN = 21.3dB 160 158 156 154 FREQUENCY (MHz) Figure 29. Small-Signal Dynamic Range vs. RF Frequency ...
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EQUIVALENT CIRCUITS V AVDD2 CM 15kΩ LI-x, LG-x Figure 30. Equivalent LNA Input Circuit AVDD2 AVDD2 10Ω LO-x, LOSW-x Figure 31. Equivalent LNA Output Circuit AVDD1 350Ω CLK+ 10kΩ AVDD1 10kΩ 350Ω CLK– Figure 32. Equivalent Clock Input Circuit AVDD2 ...
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AD9277 AVDD1 AVDD1 70kΩ 350Ω CSB Figure 38. Equivalent CSB Input Circuit VREF 6kΩ Figure 39. Equivalent VREF Circuit 100Ω RBIAS Figure 40. Equivalent RBIAS Circuit AVDD2 GAIN+ Figure 41. Equivalent GAIN+ Input Circuit AVDD2 GAIN– Figure 42. Equivalent GAIN− ...
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THEORY OF OPERATION ULTRASOUND The primary application for the AD9277 is medical ultrasound. Figure 45 shows a simplified block diagram of an ultrasound system. A critical function of an ultrasound system is the time gain control (TGC) compensation for physiological ...
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AD9277 4LO– 4LO+ RESET R LO-x FB1 R LOSW-x FB2 T/R SWITCH C S LI-x LG TRANSDUCER CHANNEL OVERVIEW Each channel contains both a TGC signal path and a CW Doppler signal path. Common to both ...
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Low value feedback resistors and the current-driving capability of the output stage allow the LNA to achieve a low input- referred noise voltage of 0.75 nV/√Hz (at a gain of 21.3 dB). This is achieved with a current consumption of ...
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AD9277 LNA Noise The short-circuit noise voltage (input-referred noise important limit on system performance. The short-circuit noise voltage for the LNA is 0.75 nV/√ gain of 21.3 dB, including the VGA noise at a VGA postamp ...
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INPUT OVERDRIVE Excellent overload behavior is of primary importance in ultrasound. Both the LNA and VGA have built-in overdrive protection and quickly recover after an overload event. Input Overload Protection As with any amplifier, voltage clamping prior to the inputs ...
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AD9277 I/Q Demodulator and Phase Shifter The I/Q demodulators consist of double-balanced passive mixers. The RF input signals are converted into currents by transconduc- tance stages that have a maximum differential input signal capability matching the LNA output full scale. ...
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LNA CHANNEL A CHANNEL H LNA Phase Compensation and Analog Beamforming Beamforming, as applied to medical ultrasound, is defined as the phase alignment and summation of signals generated from a common source but received at different times by a multielement ...
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AD9277 For CW Doppler operation, the AD9277 integrates the LNA, phase shifter, frequency conversion, and I/Q demodulation into a single package and directly yields the baseband signal. Figure simplified diagram showing the concept for four channels. The ...
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TGC OPERATION The TGC signal path is fully differential throughout to maxi- mize signal swing and reduce even-order distortion; however, the LNAs are designed to be driven from a single-ended signal source. Gain values are referenced from the single-ended LNA ...
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AD9277 Table 10. Sensitivity and Dynamic Range Trade-Offs LNA Gain Full-Scale Input Noise (V/V) (dB) Input (V p-p) (nV/√Hz) 6 15.6 0.733 0.98 8 17.9 0.550 0.86 12 21.3 0.367 0.75 1 LNA: output full scale = 4.4 V p-p ...
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PGA GAIN = 21dB 0.4 PGA GAIN = 24dB 0.3 0.2 0.1 PGA GAIN = 27dB PGA GAIN = 30dB 0 0 0.2 0.4 0.6 0.8 1.0 GAIN+ (V) Figure 57. LNA with 17.9 dB Gain Setting/VGA Full-Scale ...
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AD9277 499Ω ±0.4V DC 100Ω AT 0.8V CM GAIN+ 0.01µF AD8138 100Ω GAIN– ±0.4V DC 0.01µF AT 0.8V CM 499Ω Figure 61. Differential GAIN+, GAIN− Pin Configuration VGA Noise In a typical application, a VGA compresses a wide dynamic range ...
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ADC The AD9277 uses a pipelined ADC architecture. The quantized output from each stage is combined into a 14-bit result in the digital correction logic. The pipelined architecture permits the first stage to operate on a new input sample and ...
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AD9277 The duty cycle stabilizer uses a delay-locked loop (DLL) to create the nonsampling edge result, any changes to the sampling frequency require approximately eight clock cycles to allow the DLL to acquire and lock to the new ...
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By asserting the PDWN pin high, the AD9277 is placed into power-down mode. In this state, the device typically dissipates 5 mW. During power-down, the LVDS output drivers are placed into a high impedance state. The AD9277 returns to normal ...
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AD9277 600 EYE: ALL BITS 400 200 100 0 –100 –200 –400 –600 –1.5ns –1.0ns –0.5ns 0ns –200ps –100ps 0ps Figure 73. Data Eye for LVDS Outputs in ANSI-644 Mode with Trace Lengths of ...
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EYE: ALL BITS 400 200 0 –200 –400 –600 –1.5ns –1.0ns –0.5ns 0ns –200ps –100ps 0ps Figure 75. Data Eye for LVDS Outputs in ANSI-644 Mode with 100 Ω Termination On and Trace ...
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AD9277 Table 13. Flexible Output Test Modes Output Test Mode Bit Sequence Pattern Name 0000 Off (default) 0001 Midscale short 0010 +Full-scale short 0011 −Full-scale short 0100 Checkerboard 0101 PN sequence long 0110 PN sequence short 0111 One-/zero-word toggle 1000 ...
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SERIAL PORT INTERFACE (SPI) The AD9277 serial port interface allows the user to configure the signal chain for specific functions or operations through a structured register space provided inside the chip. The SPI offers the user added flexibility and customization, ...
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AD9277 During normal operation, CSB is used to signal to the device that SPI commands are to be received and processed. When CSB is brought low, the device processes SCLK and SDIO to execute instructions. Normally, CSB remains low until ...
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MEMORY MAP READING THE MEMORY MAP TABLE Each row in the memory map register table has eight bit loca- tions. The memory map is roughly divided into three sections: the chip configuration register map (Address 0x00 to Address 0x02), the ...
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AD9277 Table 18. AD9277 Memory Map Registers Addr. Bit 7 (Hex) Register Name (MSB) Bit 6 Chip Configuration Registers 0x00 chip_port_config 0 LSB first off (default) 0x01 chip_id 0x02 chip_grade X X Device Index and ...
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Addr. Bit 7 (Hex) Register Name (MSB) Bit 6 0x0F flex_channel_input Filter cutoff frequency control 0000 = 1.3 × 1/3 × f 0001 = 1.2 × 1/3 × f 0010 = 1.1 × 1/3 × f 0011 = 1.0 × ...
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AD9277 Addr. Bit 7 (Hex) Register Name (MSB) Bit 6 0x19 user_patt1_lsb B7 B6 0x1A user_patt1_msb B15 B14 0x1B user_patt2_lsb B7 B6 0x1C user_patt2_msb B15 B14 0x21 serial_control LSB first off (default) 0x22 serial_ch_stat ...
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APPLICATIONS INFORMATION POWER AND GROUND RECOMMENDATIONS When connecting power to the AD9277 recommended that two separate 1.8 V supplies be used: one for analog (AVDD) and one for digital (DRVDD). If only one 1.8 V supply is available, ...
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... SEATING 0.05 0.08 MAX PLANE COPLANARITY VIEW A ROTATED 90 ° CCW ORDERING GUIDE Model Temperature Range 1 AD9277BSVZ −40°C to +85°C 1 AD9277-50EBZ RoHS Compliant Part. 16.00 BSC SQ 14.00 BSC SQ 100 PIN 1 TOP VIEW (PINS DOWN) 51 ...
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NOTES Rev Page AD9277 ...
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AD9277 NOTES ©2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08181-0-7/09(0) Rev Page ...