MAX1042BETX+T Maxim Integrated Products, MAX1042BETX+T Datasheet - Page 16

• Manufacturer Part Number: MAX1042BETX+T
• Description: IC ADC/DAC 10BIT W/FIFO 36TQFN
• Manufacturer: Maxim Integrated Products
• Type: ADC, DACr

Specifications of MAX1042BETX+T

• Resolution (bits): 10 b
• Sampling Rate (per Second): 225k
• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Voltage Supply Source: Analog and Digital
• Voltage - Supply: 4.75 V ~ 5.25 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 36-TQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

10-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
Table 1. Command Byte (MSB First)
The MAX1040/MAX1042/MAX1046/MAX1048 power up
with all blocks in shutdown (including the reference). All
registers power up in state 00000000, except for the
setup register and the DAC input register. The setup
register powers up at 0010 1000 with CKSEL1 = 1 and
REFSEL1 = 1. The DAC input register powers up to
FFFh when RES_SEL is high, and it powers up to 000h
when RES_SEL is low.
The MAX1040/MAX1042/MAX1046/MAX1048 ADCs use
a fully differential successive-approximation register
(SAR) conversion technique and on-chip track-and-
hold (T/H) circuitry to convert temperature and voltage
signals into 10-bit digital results. The analog inputs
accept both single-ended and differential input signals.
Single-ended signals are converted using a unipolar
transfer function, and differential signals are converted
using a selectable bipolar or unipolar transfer function.
See the ADC Transfer Functions section for more data.
When addressing the setup, register bits 5 and 4 of the
command byte (CKSEL1 and CKSEL0, respectively)
control the ADC clock modes. See Table 5. Choose
between four different clock modes for various ways to
start a conversion and determine whether the acquisi-
tions are internally or externally timed. Select clock
mode 00 to configure CNVST/AIN_ to act as a conver-
sion start and use it to request internally timed conver-
sions, without tying up the serial bus. In clock mode 01,
use CNVST to request conversions one channel at a
time, thereby controlling the sampling speed without
tying up the serial bus. Request and start internally
X = Don’t care.
* CHESL2 bit is only valid on the MAX1040/MAX1042. Set CHSEL2 to 0 on the MAX1046/MAX1048.
** Only applicable on the MAX1042/MAX1048.
16
REGISTER NAME
Conversion*
Setup
ADC Averaging
DAC Select
Reset
GPIO Configure**
GPIO Write**
GPIO Read**
No Operation
______________________________________________________________________________________
BIT 7
1
0
0
0
0
0
0
0
0
Power-Up Default State
BIT 6
ADC Clock Modes
X
1
0
0
0
0
0
0
0
10-Bit ADC
CHSEL2
CKSEL1
BIT 5
1
0
0
0
0
0
0
CHSEL1
CKSEL0
AVGON
BIT 4
timed conversions through the serial interface by writ-
ing to the conversion register in the default clock mode,
10. Use clock mode 11 with SCLK up to 3.6MHz for
externally timed acquisitions to achieve sampling rates
up to 225ksps. Clock mode 11 disables scanning and
averaging. See Figures 6–9 for timing specifications on
how to begin a conversion.
These devices feature an active-low, end-of-conversion
output. EOC goes low when the ADC completes the last
requested operation and is waiting for the next com-
mand byte. EOC goes high when CS or CNVST go low.
EOC is always high in clock mode 11.
The MAX1040/MAX1042/MAX1046/MAX1048 use a fully
differential ADC for all conversions. When a pair of
inputs are connected as a differential pair, each input is
connected to the ADC. When configured in single-
ended mode, the positive input is the single-ended
channel and the negative input is referred to AGND.
See Figure 2.
In differential mode, the T/H samples the difference
between two analog inputs, eliminating common-mode
DC offsets and noise. IN+ and IN- are selected from the
following pairs: AIN0/AIN1, AIN2/AIN3, AIN4/AIN5,
AIN6/AIN7. AIN0–AIN3 are available on all devices.
AIN0–AIN7 are available on the MAX1040/MAX1042.
See Tables 5–8 for more details on configuring the
inputs. For the inputs that are configurable as CNVST,
REF2, and an analog input, only one function can be
used at a time.
1
0
0
0
0
0
REFSEL1
CHSEL0
NAVG1
BIT 3
Single-Ended or Differential Conversions
X
1
0
0
0
0
REFSEL0
SCAN1
NAVG0
RESET
BIT 2
X
0
0
0
0
DIFFSEL1
NSCAN1
SCAN0
SLOW
BIT 1
X
1
1
0
0
DIFFSEL0
NSCAN0
FBGON
TEMP
BIT 0
X
1
0
1
0