AD5162BRMZ100 Analog Devices Inc, AD5162BRMZ100 Datasheet - Page 14

• Manufacturer Part Number: AD5162BRMZ100
• Description: IC DGTL POT DUAL 100K I2C 10MSOP
• Manufacturer: Analog Devices Inc

Specifications of AD5162BRMZ100

• Temperature Coefficient: 35 ppm/°C Typical
• Taps: 256
• Resistance (ohms): 100K
• Number Of Circuits: 2
• Memory Type: Volatile
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 10-MSOP, Micro10™, 10-uMAX, 10-uSOP
• Resistance In Ohms: 100K
• End To End Resistance: 100kohm
• No. Of Steps: 256
• Resistance Tolerance: ± 20%
• Supply Voltage Range: 2.7V To 5.5V
• Control Interface: Serial, 3-Wire
• No. Of Pots: Dual
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD5162EVAL - BOARD EVAL FOR AD5162
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

AD5162
PROGRAMMING THE POTENTIOMETER DIVIDER
Voltage Output Operation
The digital potentiometer easily generates a voltage divider at
wiper to B and wiper to A, proportional to the input voltage at
A to B. Unlike the polarity of V
positive, voltage across A to B, W to A, and W to B can be at
either polarity.
If ignoring the effect of the wiper resistance for approximation,
connecting the A terminal to 5 V and the B terminal to ground
produces an output voltage at the wiper to B, starting at 0 V up
to 1 LSB less than 5 V. Each LSB of voltage is equal to the voltage
applied across the A and B terminals divided by the 256 positions
of the potentiometer divider. The general equation defining the
output voltage at V
voltage applied to Terminal A and Terminal B is
A more accurate calculation, which includes the effect of wiper
resistance, V
Operation of the digital potentiometer in the divider mode
results in more accurate operation over temperature. Unlike in
the rheostat mode, the output voltage is dependent mainly on
the ratio of the internal resistors R
values. Therefore, the temperature drift reduces to 15 ppm/°C.
V
V
W
W
(
(
D
D
)
)
=
W
=
Figure 35. Potentiometer Mode Configuration
, is
256
R
D
WB
R
AB
V
(
W
D
A
with respect to ground for any valid input
V
)
I
+
V
256
A
+
256
A
B
−
R
WA
D
R
DD
W
AB
WA
V
(
D
to GND, which must be
B
and R
)
V
V
B
O
WB
, not on the absolute
Rev. C | Page 14 of 20
(3)
(4)
ESD PROTECTION
All digital inputs are protected with a series of input resistors
and parallel Zener ESD structures, as shown in Figure 36 and
Figure 37. This applies to the SDI, CLK, and CS
TERMINAL VOLTAGE OPERATING RANGE
The AD5162 V
conditions for proper 3-terminal digital potentiometer opera-
tion. Supply signals present on the A, B, and W terminals that
exceed V
diodes (see Figure 38).
POWER-UP SEQUENCE
Because the ESD protection diodes limit the voltage compliance
at the A, B, and W terminals (see Figure 38), it is important to
power V
terminals; otherwise, the diode is forward-biased such that V
is powered unintentionally and may affect the rest of the user’s
circuit. The ideal power-up sequence is in the following order:
GND, V
order of powering V
important, as long as they are powered after V
Figure 38. Maximum Terminal Voltages Set by V
DD
DD
DD
, digital inputs, and then V
/GND before applying voltage to the A, B, and W
or GND are clamped by the internal forward-biased
Figure 37. ESD Protection of Resistor Terminals
DD
Figure 36. ESD Protection of Digital Pins
and GND power supply defines the boundary
A
, V
A, B, W
GND
GND
B
340Ω
, V
W
, and the digital inputs is not
LOGIC
A
, V
V
A
W
B
GND
B
DD
, V
W
digital input pins.
. The relative
DD
DD
/GND.
and GND
DD