AD5161BRM100 Analog Devices Inc, AD5161BRM100 Datasheet - Page 5

• Manufacturer Part Number: AD5161BRM100
• Description: IC POT DGTL 100K 256POS 10-MSOP
• Manufacturer: Analog Devices Inc

Specifications of AD5161BRM100

• Rohs Status: RoHS non-compliant
• Taps: 256
• Resistance (ohms): 100K
• Number Of Circuits: 1
• Temperature Coefficient: 45 ppm/°C Typical
• Memory Type: Volatile
• Interface: I²C, SPI
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 10-MSOP, Micro10™, 10-uMAX, 10-uSOP
• Resistance In Ohms: 100K

10
TIMING CHARACTERISTICS—5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ VERSIONS
V
Table 3.
Parameter
SPI INTERFACE TIMING CHARACTERISTICS
I
NOTES
1
2
3
4
5
6
7
8
9
11
DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions.
2
Typical specifications represent average readings at +25°C and V
Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic.
V
INL and DNL are measured at V
Resistor terminals A, B, W have no limitations on polarity with respect to each other.
Guaranteed by design and not subject to production test.
Measured at the A terminal. The A terminal is open circuited in shutdown mode.
P
All dynamic characteristics use V
C INTERFACE TIMING CHARACTERISTICS
See timing diagram for location of measured values. All input control voltages are specified with t
level of 1.5 V.
See timing diagrams for locations of measured values.
DD
AB
DISS
Clock Frequency
Input Clock Pulsewidth
Data Setup Time
Data Hold Time
CS Setup Time
CS High Pulsewidth
CLK Fall to CS Fall Hold Time
CLK Fall to CS Rise Hold Time
CS Rise to Clock Rise Setup
SCL Clock Frequency
t
t
t
t
t
t
t
t
t
t
BUF
HD;STA
LOW
HIGH
SU;STA
HD;DAT
SU;DAT
F
R
SU;STO
= V
= +5V ± 10%, or +3V ± 10%; V
Fall Time of Both SDA and SCL Signals
Rise Time of Both SDA and SCL Signals
is calculated from (I
Bus Free Time between STOP and START
Low Period of SCL Clock
DD
High Period of SCL Clock
Setup Time for Repeated START Condition
Hold Time (Repeated START)
Data Setup Time
Setup Time for STOP Condition
, Wiper (V
Data Hold Time
W
) = no connect.
DD
× V
DD
W
). CMOS logic level inputs result in minimum power dissipation.
DD
with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = V
= 5 V.
A
= V
6, 11
6, 10
DD
; V
(Specifications Apply to All Parts)
(Specifications Apply to All Parts)
B
= 0 V; –40°C < T
Symbol
f
t
t
t
t
t
t
t
t
f
t
t
t
t
t
t
t
t
t
t
DD
CLK
CH
DS
DH
CSS
CSW
CSH0
CSH1
CS1
SCL
1
2
3
4
5
6
7
8
9
10
= 5 V.
, t
CL
Rev. A | Page 5 of 20
A
Conditions
Clock level high or low
After this period, the first clock pulse is
generated.
< +125°C; unless otherwise noted.
R
= t
F
= 2 ns (10% to 90% of 3 V) and timed from a voltage
Min
20
5
5
15
40
0
0
10
1.3
0.6
1.3
0.6
0.6
100
0.6
DD
and V
Typ
B
= 0 V.
1
Max
25
400
50
0.9
300
300
AD5161
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
kHz
μs
μs
μs
μs
μs
μs
ns
ns
ns
μs