AD5241BRU10-REEL7 Analog Devices Inc, AD5241BRU10-REEL7 Datasheet - Page 5
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AD5241BRU10-REEL7
Manufacturer Part Number
AD5241BRU10-REEL7
Description
IC DGTL POT 256POS 14-TSSOP T/R
Manufacturer
Analog Devices Inc
Datasheet
1.AD5242BRUZ100-RL7.pdf
(20 pages)
Specifications of AD5241BRU10-REEL7
Rohs Status
RoHS non-compliant
Taps
256
Resistance (ohms)
10K
Number Of Circuits
1
Temperature Coefficient
30 ppm/°C Typical
Memory Type
Volatile
Interface
I²C, 2-Wire Serial
Voltage - Supply
2.7 V ~ 5.5 V, ±2.3 V ~ 2.7 V
Operating Temperature
-40°C ~ 105°C
Mounting Type
Surface Mount
Package / Case
14-TSSOP
Resistance In Ohms
10K
Number Of Elements
1
# Of Taps
256
Resistance (max)
10KOhm
Power Supply Requirement
Single/Dual
Interface Type
Serial (2-Wire/I2C)
Single Supply Voltage (typ)
3/5V
Dual Supply Voltage (typ)
±2.5V
Single Supply Voltage (min)
2.7V
Single Supply Voltage (max)
5.5V
Dual Supply Voltage (min)
±2.3V
Dual Supply Voltage (max)
±2.7V
Operating Temp Range
-40C to 105C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
14
Lead Free Status / Rohs Status
Not Compliant
TIMING DIAGRAMS
Data of AD5241/AD5242 is accepted from the I
Table 2.
S
where:
S = start condition
P = stop condition
A = acknowledge
X = don’t care
AD1, AD0 = Package pin programmable address bits. Must be matched with the logic states at Pins AD1 and AD0.
R/ W = Read enable at high and output to SDA. Write enable at low.
A /B = RDAC subaddress select; 0 for RDAC1 and 1 for RDAC2.
RS = Midscale reset, active high.
SD = Shutdown in active high. Same as SHDN except inverse logic.
O
D7, D6, D5, D4, D3, D2, D1, D0 = data bits.
START BY
1
MASTER
, O
0
SDA
SCL
2
= Output logic pin latched values
1
0
Slave Address Byte
1
1
0
START BY
1
SDA
SCL
MASTER
1
SLAVE ADDRESS BYTE
AD1
SDA
SCL
0
FRAME 1
P
1
AD0
t
1
1
0
1
Figure 5. Reading Data from a Previously Selected RDAC Register in Write Mode
S
AD1
R/ W
t
2
1
AD0
SLAVE ADDRESS BYTE
A
0
t
R/W
3
FRAME 1
2
ACK BY
AD5241
A /B
C bus in the following serial format.
1
Figure 4. Writing to the RDAC Serial Register
9
t
8
t
8
1
A/B
RS SD
1
Figure 3. Detail Timing Diagram
AD1
t
6
RS
Instruction Byte
AD0
Rev. C | Page 5 of 20
SD
t
INSTRUCTION BYTE
R/W
9
t
O
4
1
ACK BY
O
AD5241
FRAME 2
1
O
9
2
O
2
DATA BYTE FROM PREVIOUSLY SELECTED
D7
1
X
t
7
X
RDAC REGISTER IN WRITE MODE
D6
X
X
D5
X
S
X
ACK BY
AD5241
D4
t
5
FRAME 2
A
9
t
2
D3
D7
D7
1
D2
D6
D6
D1
D5
D5
D0
NO ACK BY
MASTER
D4
DATA BYTE
FRAME 3
Data Byte
D4
9
P
STOP BY
MASTER
D3
t
10
AD5241/AD5242
D3
D2
D1
D2
D0
D1
ACK BY
AD5241
9
STOP BY
MASTER
D0
A
P