X9421YV14IZ-2.7T1 Intersil, X9421YV14IZ-2.7T1 Datasheet - Page 6

• Manufacturer Part Number: X9421YV14IZ-2.7T1
• Description: IC XDCP SGL 64-TAP 2.5K 14-TSSOP
• Manufacturer: Intersil
• Series: XDCP™r

Specifications of X9421YV14IZ-2.7T1

• Taps: 64
• Resistance (ohms): 2.5K
• Number Of Circuits: 1
• Temperature Coefficient: 300 ppm/°C Typical
• Memory Type: Non-Volatile
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 14-TSSOP
• Resistance In Ohms: 2.5K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Write In Process
The contents of the Data Registers are saved to nonvolatile
memory when the CS pin goes from LOW to HIGH after a
complete write sequence is received by the device. The
progress of this internal write operation can be monitored by a
Write In Process bit (WIP). The WIP bit is read with a Read
Status command.
Instructions
Address/Identification (ID) Byte
The first byte sent to the X9421 from the host, following a CS
going HIGH to LOW, is called the Address or Identification
byte. The most significant four bits of the slave address are a
device type identifier, for the X9421 this is fixed as 0101[B]
(refer to Figure 2).
The least significant bit in the ID byte selects one of two
devices on the bus. The physical device address is defined
by the state of the A
serial data stream with the address input state; a successful
compare of the address bit is required for the X9421 to
successfully continue the command sequence. The A
can be actively driven by a CMOS input signal or tied to V
or V
The remaining three bits in the ID byte must be set to 110.
SS
IF WCR = 00[H] THEN V
IF WCR = 3F[H] THEN V
.
SERIAL DATA PATH
FROM INTERFACE
CIRCUITRY
0
input pin. The X9421 compares the
W
W
= V
= V
6
L
H
REGISTER 2
REGISTER 0
FIGURE 1. DETAILED POTENTIOMETER BLOCK DIAGRAM
8
0
input
REGISTER 3
REGISTER 1
CC
MODIFIED SCK
X9421
UP/DN
6
Instruction Byte
The next byte sent to the X9421 contains the instruction and
register pointer information. The four most significant bits are
the instruction. The next two bits point to one of four Data
Registers. The format is shown below in Figure 3.
The four high order bits of the instruction byte specify the
operation. The next two bits (R
four registers that is to be acted upon when a register
oriented instruction is issued. The last two bits are defined
as 0.
FIGURE 2. ADDRESS/IDENTIFICATION BYTE FORMAT
UP/DN
CLK
PARALLEL
SERIAL
BUS
INPUT
BUS
INPUT
0
REGISTER
I3
COUNTER
FIGURE 3. INSTRUCTION BYTE FORMAT
INC/DEC
DEVICE TYPE
WIPER
(WCR)
LOGIC
IDENTIFIER
1
INSTRUCTIONS
I2
0
I1
C
O
U
N
T
E
R
D
E
C
O
D
E
1
I0
1
1
REGISTER
R1
and R
SELECT
1
R0
0
) select one of the
DEVICE ADDRESS
0
0
A0
January 14, 2009
V
V
V
H
L
W
0
FN8196.4