X9271UV14Z-2.7 Intersil, X9271UV14Z-2.7 Datasheet - Page 6

• Manufacturer Part Number: X9271UV14Z-2.7
• Description: IC XDCP SGL 256TAP 50K 14-TSSOP
• Manufacturer: Intersil
• Series: XDCP™r

Specifications of X9271UV14Z-2.7

• Taps: 256
• Resistance (ohms): 50K
• Number Of Circuits: 1
• Temperature Coefficient: 300 ppm/°C Typical
• Memory Type: Non-Volatile
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 14-TSSOP
• Resistance In Ohms: 50K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PRINCIPLES OF OPERATION
Device Description
S
The X9271 supports the SPI interface hardware
conventions. The device is accessed via the SI input
with data clocked in on the rising SCK. CS must be
LOW and the HOLD and WP pins must be HIGH
during the entire operation.
The SO and SI pins can be connected together, since
they have three state outputs. This can help to reduce
system pin count.
A
The X9271 is comprised of a resistor array (See
Figure 1). The array contains the equivalent of 255
discrete resistive segments that are connected in
Figure 1. Detailed Potentiometer Block Diagram
ERIAL
RRAY
IF WCR = 00[H] THEN R
IF WCR = FF[H] THEN R
D
SERIAL DATA PATH
FROM INTERFACE
I
NTERFACE
ESCRIPTION
CIRCUITRY
W
W
= R
= R
6
L
H
REGISTER 2
REGISTER 0
(DR0)
(DR2)
BANK_0 Only
8
REGISTER 1
REGISTER 3
MODIFIED SCK
(DR1)
(DR3)
X9271
UP/DN
8
series. The physical ends of each array are equivalent
to the fixed terminals of a mechanical potentiometer
(R
At both ends of each array and between each resistor
segment is a CMOS switch connected to the wiper
(R
switch may be turned on at a time.
These switches are controlled by a Wiper Counter
Register (WCR). The 8-bits of the WCR (WCR[7:0])
are decoded to select, and enable, one of 256
switches (See Table 1).
P
There are no restrictions on the power-up or power-
down conditions of V
the potentiometer pins provided that V
more positive than or equal to V
V
always in effect.
OWER
CC
W
H
PARALLEL
BUS
INPUT
UP/DN
CLK
) output. Within each individual array only one
SERIAL
BUS
INPUT
and R
≥ V
REGISTER
COUNTER
INC/DEC
WIPER
LOGIC
-
(WCR)
H
UP AND
, V
L
inputs).
L
, V
W
D
. The V
OWN
C
O
U
N
T
E
R
D
E
C
O
D
E
CC
R
CC
and the voltages applied to
ECOMMENDATIONS
ramp rate specification is
H
, V
L
, and V
CC
R
R
R
November 22, 2005
H
L
W
is always
.
W
FN8174.2
, i.e.,