X9118TV14IZ-2.7 Intersil, X9118TV14IZ-2.7 Datasheet - Page 5

• Manufacturer Part Number: X9118TV14IZ-2.7
• Description: IC XDCP SGL 1024TAP 100K 14TSSOP
• Manufacturer: Intersil
• Series: XDCP™r

Specifications of X9118TV14IZ-2.7

• Taps: 1024
• Resistance (ohms): 100K
• Number Of Circuits: 1
• Temperature Coefficient: 300 ppm/°C Typical
• Memory Type: Non-Volatile
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 14-TSSOP
• Resistance In Ohms: 100K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ACKNOWLEDGE POLLING
The disabling of the inputs during the internal nonvolatile write
operation can be used to take advantage of the typical 5ms
EEPROM write cycle time. Once the stop condition is issued to
indicate the end of the nonvolatile write command the X9118
initiates the internal write cycle. ACK polling, Flow 1, can be
initiated immediately. This involves issuing the start condition
followed by the device slave address. If the X9118 is still busy
with the write operation no ACK will be returned. If the X9118
has completed the write operation an ACK will be returned and
the master can then proceed with the next operation.
Flow 1. ACK Polling Sequence
COMMAND COMPLETED
NONVOLATILE WRITE
ENTERACK POLLING
FROM TRANSMITTER
INSTRUCTION
ISSUE SLAVE
OPERATION?
RETURNED?
ADDRESS
FURTHER
FROM RECEIVER
PROCEED
START
ISSUE
ISSUE
DATA OUTPUT
DATA OUTPUT
ACK
YES
SCL FROM
YES
MASTER
NO
NO
5
START
FIGURE 2. ACKNOWLEDGE RESPONSE FROM RECEIVER
ISSUE STOP
ISSUE STOP
PROCEED
1
X9118
INSTRUCTION AND REGISTER DESCRIPTION
Device Addressing: Identification Byte (ID and A)
Following a start condition, the master must output the
address of the slave it is accessing. The most significant four
bits of the slave address are the device type identifier. The
ID[3:0] bits is the device ID for the X9118; this is fixed as
0101[B] (refer to Table 1).
The A[1:0] bits in the ID byte are the internal slave address.
The physical device address is defined by the state of the
A1-A0 input pins. The slave address is externally specified
by the user. The X9118 compares the serial data stream with
the address input state; a successful compare of both
address bits is required for the X9118 to successfully
continue the command sequence. Only the device which
slave address matches the incoming device address sent by
the master executes the instruction. The A1-A0 inputs can
be actively driven by CMOS input signals or tied to V
V
read or write operations.
INSTRUCTION BYTE AND REGISTER SELECTION
The next byte sent to the X9118 contains the instruction and
register pointer information. The three most significant bits
are used to provide the instruction opcode (I[2:0]). The RB
and RA bits point to one of the four registers. The format is
shown in Table 2.
Table 3 provides a complete summary of the instruction set
opcodes.
SS
. The R/W bit is the LSB and is used to set the device for
8
ACKNOWLEDGE
9
December 4, 2009
CC
FN8161.4
or