X9258TS24I-2.7T1 Intersil, X9258TS24I-2.7T1 Datasheet - Page 4
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X9258TS24I-2.7T1
Manufacturer Part Number
X9258TS24I-2.7T1
Description
IC XDCP QUAD 256TAP 100K 24-SOIC
Manufacturer
Intersil
Series
XDCP™r
Datasheet
1.X9258US24.pdf
(20 pages)
Specifications of X9258TS24I-2.7T1
Taps
256
Resistance (ohms)
100K
Number Of Circuits
4
Temperature Coefficient
300 ppm/°C Typical
Memory Type
Non-Volatile
Interface
I²C, 2-Wire Serial
Voltage - Supply
2.7 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
24-SOIC (7.5mm Width)
Resistance In Ohms
100K
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
initiate data transfers and provide the clock for both transmit
and receive operations. Therefore, the X9258 will be
considered a slave device in all applications.
Clock and Data Conventions
Data states on the SDA line can change only during SCL
LOW periods (t
are reserved for indicating start and stop conditions.
Start Condition
All commands to the X9258 are preceded by the start
condition, which is a HIGH to LOW transition of SDA while
SCL is HIGH (t
SDA and SCL lines for the start condition and will not
respond to any command until this condition is met.
Stop Condition
All communications must be terminated by a stop condition,
which is a LOW to HIGH transition of SDA while SCL is
HIGH.
Acknowledge
Acknowledge is a software convention used to provide a
positive handshake between the master and slave devices
on the bus to indicate the successful receipt of data. The
transmitting device, either the master or the slave, will
release the SDA bus after transmitting 8 bits. The master
generates a ninth clock cycle and during this period the
receiver pulls the SDA line LOW to acknowledge that it
successfully received the 8 bits of data.
The X9258 will respond with an acknowledge after
recognition of a start condition and its slave address and
once again after successful receipt of the command byte. If
the command is followed by a data byte, the X9258 will
respond with a final acknowledge.
Array Description
The X9258 is comprised of four resistor arrays. Each array
contains 255 discrete resistive segments that are connected
in series. The physical ends of each array are equivalent to
the fixed terminals of a mechanical potentiometer (V
and V
At both ends of each array and between each resistor
segment is a CMOS switch connected to the wiper (V
output. Within each individual array only one switch may be
turned on at a time. These switches are controlled by the
Wiper Counter Register (WCR). The 8 bits of the WCR are
decoded to select, and enable, one of 256 switches.
The WCR may be written directly, or it can be changed by
transferring the contents of one of four associated data
registers into the WCR. These data registers and the WCR
can be read and written by the host system.
L
/R
L
inputs).
HIGH
LOW
). SDA state changes during SCL HIGH
). The X9258 continuously monitors the
4
H
W
/R
)
H
X9258
Device Addressing
Following a start condition the master must output the
address of the slave it is accessing. The most significant
4 bits of the slave address are the device type identifier
(refer to Figure 1). For the X9258 this is fixed as 0101[B].
The next 4 bits of the slave address are the device address.
The physical device address is defined by the state of the A0
thru A3 inputs. The X9258 compares the serial data stream
with the address input state; a successful compare of all
4 address bits is required for the X9258 to respond with an
acknowledge. The A
by CMOS input signals or tied to V
Acknowledge Polling
The disabling of the inputs (during the internal nonvolatile
write operation), can be used to take advantage of the
typical 5ms nonvolatile write cycle time. Once the stop
condition is issued to indicate the end of the nonvolatile write
command, the X9258 initiates the internal write cycle. ACK
polling can be initiated immediately. This involves issuing the
start condition followed by the device slave address. If the
X9258 is still busy with the write operation, no ACK will be
returned. If the X9258 has completed the write operation an
ACK will be returned and the master can then proceed with
the next operation.
0
DEVICE TYPE
IDENTIFIER
1
FIGURE 1. SLAVE ADDRESS
0
0
thru A
1
3
inputs can be actively driven
A3
DEVICE ADDRESS
CC
A2
or V
SS
A1
.
A0
April 14, 2011
FN8168.5