X9409WV24I-2.7 Intersil, X9409WV24I-2.7 Datasheet - Page 3
![IC DCP QUAD 10K 64TP 24TSSOP](/photos/6/65/66570/20-24-tssop_sml.jpg)
X9409WV24I-2.7
Manufacturer Part Number
X9409WV24I-2.7
Description
IC DCP QUAD 10K 64TP 24TSSOP
Manufacturer
Intersil
Series
XDCP™r
Datasheet
1.X9409WS24ZT1.pdf
(20 pages)
Specifications of X9409WV24I-2.7
Taps
64
Resistance (ohms)
10K
Number Of Circuits
4
Temperature Coefficient
300 ppm/°C Typical
Memory Type
Non-Volatile
Interface
I²C, 2-Wire Serial
Voltage - Supply
2.7 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
24-TSSOP
Resistance In Ohms
10K
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
X9409WV24I-2.7T1
Manufacturer:
XICOR
Quantity:
20 000
Part Number:
X9409WV24I-2.7T2
Manufacturer:
XICOR
Quantity:
20 000
PIN CONFIGURATION
PRINCIPLES OF OPERATION
The X9409 is a highly integrated microcircuit
incorporating four resistor arrays and their associated
registers and counters and the serial interface logic
providing direct communication between the host and
the XDCP potentiometers.
Serial Interface
The X9409 supports a bidirectional bus oriented
protocol. The protocol defines any device that sends
data onto the bus as a transmitter and the receiving
device as the receiver. The device controlling the
transfer is a master and the device being controlled is
the slave. The master will always initiate data transfers
and provide the clock for both transmit and receive
operations. Therefore, the X9409 will be considered a
slave device in all applications.
Clock and Data Conventions
Data states on the SDA line can change only during
SCL LOW periods (t
SCL HIGH are reserved for indicating start and stop
conditions.
Start Condition
All commands to the X9409 are preceded by the start
condition, which is a HIGH to LOW transition of SDA
while SCL is HIGH (t
monitors the SDA and SCL lines for the start condition
and will not respond to any command until this
condition is met.
V
V
V
V
V
W0
V
W1
H0
H1
L0
L1
/R
/R
LOW
/R
/R
SDA
V
/R
/R
V
HIGH
WP
CC
W0
W1
H0
A
A
H1
SS
L0
L1
2
1
). SDA state changes during
3
). The X9409 continuously
10
11
12
1
2
3
4
5
6
7
8
9
X9409
SOIC
13
14
24
23
22
21
20
19
18
17
16
15
NC
V
V
V
A
NC
A
SCL
V
V
V
NC
L3
H3
W3
0
3
L2
H2
W2
/R
/R
/R
/R
/R
/R
L3
L2
H3
H2
W3
W2
X9409
Stop Condition
All communications must be terminated by a stop
condition, which is a LOW to HIGH transition of SDA
while SCL is HIGH.
Acknowledge
Acknowledge is a software convention used to provide
a positive handshake between the master and slave
devices on the bus to indicate the successful receipt of
data. The transmitting device, either the master or the
slave, will release the SDA bus after transmitting eight
bits. The master generates a ninth clock cycle and
during this period the receiver pulls the SDA line LOW
to acknowledge that it successfully received the eight
bits of data.
The X9409 will respond with an acknowledge after
recognition of a start condition and its slave address
and once again after successful receipt of the
command byte. If the command is followed by a data
byte the X9409 will respond with a final acknowledge.
Array Description
The X9409 is comprised of four resistor arrays. Each
array contains 63 discrete resistive segments that are
connected in series. The physical ends of each array
are equivalent to the fixed terminals of a mechanical
potentiometer (V
At both ends of each array and between each resistor
segment is a CMOS switch connected to the wiper
(V
switch may be turned on at a time. These switches are
V
V
V
V
V
W1
W2
V
W
H1
H2
L1
L2
/R
/R
/R
/R
/R
SDA
/R
/R
SCL
V
NC
W1
W2
W
SS
A
H1
H2
A
L1
L2
1
3
) output. Within each individual array only one
10
11
12
1
2
3
4
5
6
7
8
9
H
TSSOP
X9409
/R
H
and V
13
14
24
23
22
21
20
19
18
17
16
15
L
/R
WP
A
V
V
V
V
NC
V
V
V
A
NC
2
W0
H0
L0
CC
L3
H3
W3
0
L
inputs).
/R
/R
/R
/R
/R
/R
L0
L3
H0
H3
W0
W3
October 12, 2006
FN8192.4