MPC8309VMAHFCA Freescale Semiconductor, MPC8309VMAHFCA Datasheet - Page 17

• Manufacturer Part Number: MPC8309VMAHFCA
• Description: 417/333/233 MP Std Tmp
• Manufacturer: Freescale Semiconductor

Specifications of MPC8309VMAHFCA

• Processor Series: MPC8309
• Core: e300c3
• Data Bus Width: 32 bit
• Data Ram Size: 512 MB
• Interface Type: USB, CAN, UART, PCI
• Maximum Clock Frequency: 417 MHz
• Number Of Programmable I/os: 56
• Operating Supply Voltage: - 0.3 V to + 1.26 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Operating Temperature Range: 0 C to + 105 C
• Processor To Be Evaluated: MPC8309
• Supply Current (max): 5 uA
• Lead Free Status / Rohs Status: Details

Freescale Semiconductor
At recommended operating conditions with GV
MCS output setup with respect to MCK
MCS output hold with respect to MCK
MCK to MDQS Skew
MDQ/MDM output setup with respect to MDQS
MDQ/MDM output hold with respect to MDQS
MDQS preamble start
MDQS epilogue end
Notes:
1. The symbols used for timing specifications follow the pattern of t
2. All MCK/MCK referenced measurements are made from the crossing of the two signals ±0.1 V.
3. ADDR/CMD includes all DDR SDRAM output signals except MCK/MCK, MCS, and MDQ/MDM/MDQS. For the ADDR/CMD
4. Note that t
5. Determined by maximum possible skew between a data strobe (MDQS) and any corresponding bit of data (MDQ), or data
6. t
inputs and t
(DD) from the rising or falling edge of the reference clock (KH or KL) until the output went invalid (AX or DX). For example,
t
(A) are setup (S) or output valid time. Also, t
(K) goes low (L) until data outputs (D) are invalid (X) or data output hold time.
setup and hold specifications, it is assumed that the Clock Control register is set to adjust the memory clocks by 1/2 applied
cycle.
from the rising edge of the MCK(n) clock (KH) until the MDQS signal is valid (MH). t
of the DQSS override bits in the TIMING_CFG_2 register. This is typically set to the same delay as the clock adjusts in the
CLK_CNTL register. The timing parameters listed in the table assume that these 2 parameters have been set to the same
adjustment value. See the MPC8309 PowerQUICC II Pro Integrated Communications Processor Reference Manual for a
description and understanding of the timing modifications enabled by use of these bits.
mask (MDM). The data strobe should be centered inside of the data eye at the pins of the microprocessor.
DDKHAS
DDKHMP
MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1
symbolizes DDR timing (DD) for the time t
follows the symbol conventions described in note 1.
DDKHMH
(first two letters of functional block)(reference)(state)(signal)(state)
Parameter
follows the symbol conventions described in note 1. For example, t
Table 16. DDR2 SDRAM Output AC Timing Specifications (continued)
333 MHz
266 MHz
333 MHz
266 MHz
333 MHz
266 MHz
333 MHz
266 MHz
DD
of 1.8V ± 100mV.
DDKLDX
MCK
Symbol
t
t
t
t
t
t
t
t
t
DDKHDS,
DDKHDX,
DDKHMH
DDKHMP
DDKHME
DDKHCS
DDKHCX
DDKLDS
DDKLDX
symbolizes DDR timing (DD) for the time t
memory clock reference (K) goes from the high (H) state until outputs
1
(first two letters of functional block)(signal)(state)(reference)(state)
for outputs. Output hold time can be read as DDR timing
0.75 x t
0.4 x t
1100
–0.6
Min
900
2.4
2.5
2.4
2.5
0.8
0.9
MCK
MCK
DDKHMH
DDKHMH
0.6 x t
Max
0.6
—
—
—
—
—
can be modified through control
describes the DDR timing (DD)
MCK
MCK
memory clock reference
Unit
ns
ns
ns
ns
ps
ns
ns
DDR2 SDRAM
Note
3
3
4
5
5
6
6
for
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