MPC8309VMAHFCA Freescale Semiconductor, MPC8309VMAHFCA Datasheet - Page 67

• Manufacturer Part Number: MPC8309VMAHFCA
• Description: 417/333/233 MP Std Tmp
• Manufacturer: Freescale Semiconductor

Specifications of MPC8309VMAHFCA

• Processor Series: MPC8309
• Core: e300c3
• Data Bus Width: 32 bit
• Data Ram Size: 512 MB
• Interface Type: USB, CAN, UART, PCI
• Maximum Clock Frequency: 417 MHz
• Number Of Programmable I/os: 56
• Operating Supply Voltage: - 0.3 V to + 1.26 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Operating Temperature Range: 0 C to + 105 C
• Processor To Be Evaluated: MPC8309
• Supply Current (max): 5 uA
• Lead Free Status / Rohs Status: Details

Configuration chapter in the MPC8309 PowerQUICC II Pro Integrated Communications Processor
Reference Manual.
The qe_clk frequency is determined by the QUICC Engine PLL multiplication factor (RCWL[CEPMF])
and the QUICC Engine PLL division factor (RCWL[CEPDF]) as the following equation:
For more information, see the QUICC Engine PLL Multiplication Factor section and the “QUICC Engine
PLL Division Factor” section in the MPC8309 PowerQUICC II Pro Integrated Communications
Processor Reference Manual for more information.
The DDR SDRAM memory controller operates with a frequency equal to twice the frequency of csb_clk.
Note that ddr_clk is not the external memory bus frequency; ddr_clk passes through the DDR clock divider
(2) to create the differential DDR memory bus clock outputs (MCK and MCK). However, the data rate
is the same frequency as ddr_clk.
The local bus memory controller operates with a frequency equal to the frequency of csb_clk. Note that
lbc_clk is not the external local bus frequency; lbc_clk passes through the LBC clock divider to create the
external local bus clock outputs (LCLK). The LBC clock divider ratio is controlled by LCRR[CLKDIV].
For more information, see the LBC Bus Clock and Clock Ratios section in the MPC8309 PowerQUICC
II Pro Integrated Communications Processor Reference Manual.
In addition, some of the internal units may be required to be shut off or operate at lower frequency than
the csb_clk frequency. These units have a default clock ratio that can be configured by a memory mapped
register after the device comes out of reset.
The following table specifies which units have a configurable clock frequency. For detailed description,
refer to the “System Clock Control Register (SCCR)” section in the MPC8309 PowerQUICC II Pro
Integrated Communications Processor Reference Manual.
The following table provides the maximum operating frequencies for the MPC8309 MAPBGA under
recommended operating conditions (see
Freescale Semiconductor
I2C,SDHC, USB, DMA Complex
e300 core frequency (core_clk)
Coherent system bus frequency (csb_clk)
QUICC Engine frequency (qe_clk)
MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1
Setting the clock ratio of these units must be performed prior to any access
to them.
Unit
Characteristic
qe_clk = (QE_CLK_IN × CEPMF)  (1 + CEPDF)
Table 57. Operating Frequencies for MAPBGA
1
Table 56. Configurable Clock Units
Table
Default Frequency
2).
csb_clk
NOTE
Max Operating Frequency
Off, csb_clk, csb_clk/2, csb_clk/3
417
167
233
Options
MHz
MHz
MHz
Unit
Clocking
Eqn. 3
67