PIC18F67K22-I/MR Microchip Technology, PIC18F67K22-I/MR Datasheet - Page 219
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PIC18F67K22-I/MR
Manufacturer Part Number
PIC18F67K22-I/MR
Description
128kB Flash, 4kB RAM, 1kB EE, NanoWatt XLP, GP 64 QFN 9x9x0.9mm TUBE
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheet
1.PIC18F65K22-EMR.pdf
(550 pages)
Specifications of PIC18F67K22-I/MR
Core Processor
PIC
Core Size
8-Bit
Speed
64MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
128KB (64K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 16x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-VFQFN Exposed Pad
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F67K22-I/MRRSL
Manufacturer:
FSC
Quantity:
250
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16.5.4
When Timer3/5/7 Gate Single Pulse mode is enabled,
it is possible to capture a single pulse gate event.
Timer3/5/7 Gate Single Pulse mode is first enabled by
setting the TxGSPM bit (TxGCON<4>). Next, the
TxGGO/TxDONE bit (TxGCON<3>) must be set.
The Timer3/5/7 will be fully enabled on the next incre-
menting edge. On the next trailing edge of the pulse,
the TxGGO/TxDONE bit will automatically be cleared.
FIGURE 16-4:
2009-2011 Microchip Technology Inc.
Timer3/5/7
TMRxGIF
TMRxGE
TxGSPM
TxDONE
TxGPOL
TxGGO/
TxGVAL
TxG_IN
TxCKI
TIMER3/5/7 GATE SINGLE PULSE
MODE
TIMER3/5/7 GATE SINGLE PULSE MODE
Cleared by Software
N
Counting Enabled on
Set by Software
Rising Edge of TxG
N + 1
PIC18F87K22 FAMILY
No other gate events will be allowed to increment
Timer3/5/7 until the TxGGO/TxDONE bit is once again
set in software.
Clearing the TxGSPM bit also will clear the TxGGO/
TxDONE bit. (For timing details, see
Simultaneously enabling the Toggle mode and the
Single Pulse mode will permit both sections to work
together. This allows the cycle times on the Timer3/5/7
gate source to be measured. (For timing details, see
Figure
16-5.)
Set by Hardware on
Falling Edge of TxGVAL
Cleared by Hardware on
Falling Edge of TxGVAL
N + 2
DS39960D-page 219
Figure
Cleared by
Software
16-4.)
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