AD5203AN10 Analog Devices Inc, AD5203AN10 Datasheet - Page 9

• Manufacturer Part Number: AD5203AN10
• Description: IC DGTL POT QUAD 64POS 24-DIP
• Manufacturer: Analog Devices Inc

Specifications of AD5203AN10

• Rohs Status: RoHS non-compliant
• Taps: 64
• Resistance (ohms): 10K
• Number Of Circuits: 4
• Temperature Coefficient: 700 ppm/°C Typical
• Memory Type: Volatile
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Through Hole
• Package / Case: 24-DIP (0.300", 7.62mm)
• Resistance In Ohms: 10K
• Number Of Elements: 4
• # Of Taps: 64
• Resistance (max): 10KOhm
• Power Supply Requirement: Single
• Interface Type: Serial (3-Wire/SPI)
• Single Supply Voltage (typ): 3/5V
• Dual Supply Voltage (typ): Not RequiredV
• Single Supply Voltage (min): 2.7V
• Single Supply Voltage (max): 5.5V
• Dual Supply Voltage (min): Not RequiredV
• Dual Supply Voltage (max): Not RequiredV
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Through Hole
• Pin Count: 24
• Lead Free Status / Rohs Status: Not Compliant

OPERATION
The AD5203 provides a quad channel, 64-position digitally-
controlled variable resistor (VR) device. Changing the pro-
grammed VR settings is accomplished by clocking in an 8-bit
serial data word into the SDI (Serial Data Input) pin. The for-
mat of this data word is two address bits, MSB first, followed by
six data bits, MSB first. Table I provides the serial register data
word format. The AD5203 has the following address assign-
ments for the ADDR decode, which determines the location of
VR latch receiving the serial register data in Bits B5 through B0:
VR outputs can be changed one at a time in random sequence.
The serial clock running at 10 MHz makes it possible to load all
four VRs in under 3.2 s (8
exact timing requirements are shown in Figure 1.
The AD5203 resets to a midscale by asserting the RS pin, sim-
plifying initial conditions at power-up. Both parts have a power
shutdown SHDN pin that places the RDAC in a zero power
consumption state where terminals Ax are open-circuited and
the wiper Wx is connected to Bx, resulting in only leakage cur-
rents being consumed in the VR structure. In shutdown mode
the VR latch settings are maintained so that, returning to opera-
tional mode from power shutdown, the VR settings return to
their previous resistance values.
PROGRAMMING THE VARIABLE RESISTOR
Rheostat Operation
The nominal resistance of the RDAC between Terminals A and
B are available with values of 10 k , and 100 k . The final
digits of the part number determine the nominal resistance
value, e.g., 10 k = 10; 100 k = 100. The nominal resistance
(R
terminal, plus the B terminal contact. The 6-bit data word in
the RDAC latch is decoded to select one of the 64 possible
settings. The wiper’s first connection starts at the B terminal for
data 00
tance of 45 . The second connection (10 k part) is the first
REV. 0
AB
) of the VR has 64 contact points accessed by the wiper
H
. This B–terminal connection has a wiper contact resis-
SHDN
Figure 34. Equivalent RDAC Circuit
D5
D4
D3
D2
D1
D0
VR# = A1
DECODER
LATCH
RDAC
&
4
R
R
R
R
R
S
S
S
S
S
2 + A0 + 1
= R
100 ns) for the AD5203. The
AB
/64
Ax
Wx
Bx
–9–
tap point located at 201
= 156
tap point representing 312 + 45 = 357
LSB data value increase moves the wiper up the resistor ladder
until the last tap point is reached at 9889 . The wiper does not
directly connect to the B Terminal. See Figure 34 for a simpli-
fied diagram of the equivalent RDAC circuit.
The general transfer equation that determines the digitally pro-
grammed output resistance between Wx and Bx is:
where Dx is the data contained in the 6-bit RDACx latch and
R
For example, when V
following output resistance values will be set for the following
RDAC latch codes (applies to the 10K potentiometer):
D (DEC) R
63
32
1
0
Note that in the zero-scale condition a finite wiper resistance of
45
between W and B in this state to a maximum value of 5 mA to
avoid degradation or possible destruction of the internal switch
contact.
Like the mechanical potentiometer the RDAC replaces, it is
totally symmetrical. The resistance between the wiper W and
terminal A also produces a digitally controlled resistance R
When these terminals are used the B–terminal should be tied to
the wiper. Setting the resistance value for R
mum value of resistance and decreases as the data loaded in the
latch is increased in value. The general transfer equation for this
operation is:
where Dx is the data contained in the 6-bit RDACx latch and
R
V
output resistance values will be set for the following RDAC
latch codes:
D (DEC)
63
32
1
0
The typical distribution of R
within 1%. However, device-to-device matching is process-lot-
dependent, having a 30% variation. The change in R
temperature has a 700 ppm/ C temperature coefficient.
BA
BA
A
= 0 V and B–terminal is tied to the wiper W, the following
R
R
is the nominal end-to-end resistance.
is the nominal end-to-end resistance. For example, when
is present. Care should be taken to limit the current flow
WB
WA
(Dx) = (Dx)/64
(Dx) = (64-Dx)/64 R
+ 45 )] for data 01
9889
5045
201
45
WB
R
201
5045
9889
10045
( )
WA
B
( )
= 0 V and A–terminal is open circuit the
Output State
Full-Scale
Midscale (RS = 0 Condition)
1 LSB
Zero-Scale (Wiper Contact Resistance)
R
[= R
BA
BA
H
from channel to channel matches
. The third connection is the next
+ R
BA
BA
Midscale (RS = 0 Condition)
1 LSB
(nominal resistance)/64 + R
Output State
Full-Scale
Zero-Scale
+ R
W
W
for data 02
WA
starts at a maxi-
AD5203
H
. Each
BA
with
WA
.
(1)
(2)
W