AD5260BRU200-REEL7 Analog Devices Inc, AD5260BRU200-REEL7 Datasheet - Page 3

• Manufacturer Part Number: AD5260BRU200-REEL7
• Description: IC DGTL POT SNGL 256POS 14-TSSOP
• Manufacturer: Analog Devices Inc

Specifications of AD5260BRU200-REEL7

• Rohs Status: RoHS non-compliant
• Taps: 256
• Resistance (ohms): 200K
• Number Of Circuits: 1
• Temperature Coefficient: 35 ppm/°C Typical
• Memory Type: Volatile
• Interface: 4-Wire SPI Serial
• Voltage - Supply: 4.5 V ~ 16.5 V, ±4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 14-TSSOP
• Resistance In Ohms: 200K
• Other names: AD5260BRU200REEL7

Parameter
INTERFACE TIMING CHARACTERISTICS apply to all parts
NOTES
The AD5260/AD5262 contains 1,968 transistors. Die Size: 89 mil. × 105 mil. 9,345 sq. mil.
10
11
12
13
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS
(T
V
V
V
V
A
Digital Inputs and Output Voltage to GND . . . . . . . 0 V, 7 V
Operating Temperature Range . . . . . . . . . . . . –40°C to +85°C
Maximum Junction Temperature (T
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
REV. 0
1
2
3
4
5
6
7
8
9
Typicals represent average readings at 25°C and V
Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions.
R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. I
V
INL and DNL are measured at V
specification limits of ± 1 LSB maximum are Guaranteed Monotonic operating conditions.
Resistor terminals A, B, W have no limitations on polarity with respect to each other.
Guaranteed by design and not subject to production test.
Measured at the Ax terminals. All Ax terminals are open-circuit in shutdown mode.
Worst-case supply current consumed when input all logic-input levels set at 2.4 V, standard characteristic of CMOS logic.
P
All dynamic characteristics use V
Measured at a V
See timing diagram for location of measured values. All input control voltages are specified with t
Switching characteristics are measured using V
Propagation delay depends on value of V
DD
SS
DD
A
X
A
Clock Frequency
Input Clock Pulsewidth
Data Setup Time
Data Hold Time
CLK to SDO Propagation Delay
CS Setup Time
CS High Pulsewidth
Reset Pulsewidth
CLK Fall to CS Rise Hold Time
CS Rise to Clock Rise Setup
Intermittent
Continuous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 5 mA
DISS
, V
AB
= 25°C, unless otherwise noted.)
– B
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V, –7 V
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +15 V
to V
= V
B
is calculated from (I
, V
X
DD
, A
SS
W
, Wiper (V
X
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 V
– W
W
2
pin where an adjacent V
X
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 mA
, B
W
) = No connect.
X
DD
– W
V
X
DD
W
DD
with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = V
). CMOS logic level inputs result in minimum power dissipation.
= +5 V, V
DD
13
W
J MAX
, R
pin is making a full-scale voltage change.
1
SS
L
L
, and C
= 5 V.
= –5 V, V
) . . . . . . . . . . . 150°C
DD
= +5 V, V
Symbol
f
t
t
t
t
t
t
t
t
t
CLK
L
CH
DS
DH
PD
CSS
CSW
RS
CSH
CS1
.
, t
L
= +5 V.
CL
SS
= –5 V.
SS
, V
Conditions
Clock level high or low
R
DD
L
= 1 kΩ, C
–3–
6, 12
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . 300°C
Thermal Resistance
NOTES
1
2
3
Stresses above those listed under Absolute Maximum Ratings may cause permanent
damage to the device. This is a stress rating only; functional operation of the device
at these or any other conditions above those listed in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
Maximum terminal current is bounded by the maximum current handling of the
switches, maximum power dissipation of the package, and maximum applied
voltage across any two of the A, B, and W terminals at a given resistance setting.
Package Power Dissipation = (T
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . 215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
TSSOP-14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206°C/W
TSSOP-16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C/W
L
< 20pF
R
= t
F
= 2ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V.
3
θ
JA
J MAX
W
= V
Min
20
10
10
1
5
20
50
0
10
– T
DD
/R for both V
A
)/ θ
JA
Typ
AD5260/AD5262
DD
DD
= +5 V, V
and V
Max
25
160
B
= 0V. DNL
SS
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
= –5 V.