AD5260BRU200-REEL7 Analog Devices Inc, AD5260BRU200-REEL7 Datasheet - Page 8

• Manufacturer Part Number: AD5260BRU200-REEL7
• Description: IC DGTL POT SNGL 256POS 14-TSSOP
• Manufacturer: Analog Devices Inc

Specifications of AD5260BRU200-REEL7

• Rohs Status: RoHS non-compliant
• Taps: 256
• Resistance (ohms): 200K
• Number Of Circuits: 1
• Temperature Coefficient: 35 ppm/°C Typical
• Memory Type: Volatile
• Interface: 4-Wire SPI Serial
• Voltage - Supply: 4.5 V ~ 16.5 V, ±4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 14-TSSOP
• Resistance In Ohms: 200K
• Other names: AD5260BRU200REEL7

All digital inputs are protected with a series input resistor and
parallel Zener ESD structure as shown in Figure 6. This applies
to digital input pins CS, SDI, SDO, PR, SHDN, and CLK.
LAYOUT AND POWER SUPPLY BYPASSING
It is a good practice to employ compact, minimum-lead length
layout design. The leads to the input should be as direct as pos-
sible with a minimum conductor length. Ground paths should
have low resistance and low inductance.
Similarly, it is also a good practice to bypass the power supplies
with quality capacitors for optimum stability. Supply leads to the
device should be bypassed with 0.01 mF–0.1 mF disc or chip ceram-
ics capacitors. Low-ESR 1 mF to 10 mF tantalum or electrolytic
capacitors should also be applied at the supplies to minimize any
transient disturbance (see Figure 8). Notice the digital ground
should also be joined remotely to the analog ground to minimize
the ground bounce.
TERMINAL VOLTAGE OPERATING RANGE
The AD5260/AD5262 positive V
supply defines the boundary conditions for proper 3-terminal
digital potentiometer operation. Supply signals present on termi-
nals A, B, and W that exceed V
internal forward biased diodes (see Figure 9).
The ground pin of the AD5260/AD5262 device is primarily used
as a digital ground reference, which needs to be tied to the PCB’s
common ground. The digital input control signals to the AD5260/
AD5262 must be referenced to the device ground pin (GND),
and must satisfy the logic level defined in the specification table
AD5260/AD5262
Figure 9. Maximum Terminal Voltages Set by V
Figure 7. ESD Protection of Resistor Terminals
Figure 6. ESD Protection of Digital Pins
V
V
Figure 8. Power Supply Bypassing
DD
SS
C3
C4
A, B, W
10 F
10 F
340
C1
C2
V
0.1 F
0.1 F
SS
DD
DD
or V
LOGIC
and negative V
SS
will be clamped by the
V
V
DD
SS
GND
V
A
W
B
V
DD
SS
SS
DD
power
and V
SS
–8–
of this data sheet. An internal level shift circuit ensures that the
common-mode voltage range of the three terminals extends
from V
POWER-UP SEQUENCE
Since there are diodes to limit the voltage compliance at termi-
nals A, B, and W (see Figure 9), it is important to power V
first before applying any voltage to terminals A, B, and W. Other-
wise, the diode will be forward biased such that V
powered unintentionally and may affect the rest of the user’s circuit.
The ideal power-up sequence is in the following order: GND,
V
V
are powered after V
Daisy-Chain Operation
The serial-data output (SDO) pin contains an open drain
n-channel FET. This output requires a pull-up resistor to trans-
fer data to the next package’s SDI pin. This allows for daisy
chaining several RDACs from a single processor serial data line.
The pull-up resistor termination voltage can be larger than the V
supply voltage. It is recommended to increase the Clock period
when using a pull-up resistor to the SDI pin of the following device
in series because capacitive loading at the daisy-chain node
SDO-SDI between devices may induce time delay to subsequent
devices. Users should be aware of this potential problem to achieve
data transfer successfully (see Figure 10). If two AD5260s are daisy-
chained, this requires a total of 16 bits of data. The first 8 bits,
complying with the format shown in Table I, go to U2, and the
second 8 bits with the same format go to U1. The CS should be
kept low until all 16 bits are clocked into their respective serial
registers, and the CS is then pulled high to complete the operation.
RDAC STRUCTURE
The RDAC contains a string of equal resistor segments, with an
array of analog switches, that act as the wiper connection. The
number of positions is the resolution of the device. The AD5260/
AD5262 have 256 connection points allowing it to provide better
than 0.4% set-ability resolution. Figure 11 shows an equivalent
structure of the connections between the three terminals that
make up one channel of the RDAC. The SW
always be ON, while one of the switches SW(0) to SW(2
will be ON one at a time depending on the resistance position
decoded from the data bits. Since the switch is not ideal, there is
a 60 W wiper resistance, R
supply voltage and temperature. The lower the supply voltage, the
higher the wiper resistance. Similarly, the higher the temperature,
the higher the wiper resistance. Users should be aware of the
contribution of the wiper resistance when accurate prediction of
the output resistance is needed.
DD
A
, V
, V
B
, V
SS
SS
, V
to V
W
SCLK SS
, and Digital Inputs is not important as long as they
C
Figure 10. Daisy-Chain Configuration
L
, Digital Inputs, and V
DD
MOSI
regardless of the digital input level.
DD
/V
SDI
AD5260
CS CLK
SS
U1
W
.
SDO
. Wiper resistance is a function of
V
DD
2.2k
R
A/B/W
P
. The order of powering
SDI
AD5260
CS CLK
U2
A
SDO
and SW
DD
/V
SS
B
will
N
will be
REV. 0
DD
– 1)
/V
DD
SS