X9317US8 Intersil, X9317US8 Datasheet

IC DIGITAL POT 50K 100TP 8SOIC

X9317US8

Manufacturer Part Number
X9317US8
Description
IC DIGITAL POT 50K 100TP 8SOIC
Manufacturer
Intersil
Series
XDCP™r
Datasheet

Specifications of X9317US8

Taps
100
Resistance (ohms)
50K
Number Of Circuits
1
Temperature Coefficient
300 ppm/°C Typical
Memory Type
Non-Volatile
Interface
Up/Down (3-Wire)
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
8-SOIC (3.9mm Width)
Resistance In Ohms
50K
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

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Company
Part Number
Manufacturer
Quantity
Price
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Digitally Controlled Potentiometer
(XDCP™)
The Intersil X9317 is a digitally controlled potentiometer
(XDCP™). The device consists of a resistor array, wiper
switches, a control section, and nonvolatile memory. The
wiper position is controlled by a 3-wire interface.
The potentiometer is implemented by a resistor array
composed of 99 resistive elements and a wiper switching
network. Between each element and at either end are tap
points accessible to the wiper terminal. The position of the
wiper element is controlled by the CS, U/D, and INC inputs.
The position of the wiper can be stored in nonvolatile
memory and then be recalled upon a subsequent power-up
operation.
The device can be used as a three-terminal potentiometer
for voltage control or as a two-terminal variable resistor for
current control in a wide variety of applications.
Pinouts
(8 LD PDIP, 8 LD SOIC, 8 LD MSOP)
V
V
INC
U/D
INC
U/D
R
CS
CC
SS
H
1
2
3
4
1
2
3
4
(8 LD TSSOP)
TOP VIEW
TOP VIEW
®
X9317
X9317
X9317
X9317
1
8
7
6
5
Data Sheet
8
7
6
5
V
CS
R
R
R
R
V
R
CC
L
W
L
W
SS
H
XDCP is a trademark of Intersil Americas, Inc. Copyright Intersil Americas Inc. 2004-2005, 2008, 2009. All Rights Reserved
1-888-INTERSIL or 1-888-468-3774
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
Low Noise, Low Power, 100 Taps
Features
• Solid-State Potentiometer
• 3-Wire Serial Up/Down Interface
• 100 Wiper Tap Points
• 99 Resistive Elements
• Low Power CMOS
• High Reliability
• R
• Packages
• Pb-Free Available (RoHS Compliant)
Applications
• LCD Bias Control
• DC Bias Adjustment
• Gain and Offset Trim
• Laser Diode Bias Control
• Voltage Regulator Output Control
- Wiper Position Stored in Nonvolatile Memory and
- Temperature Compensated
- End-to-end Resistance Range ±20%
- V
- Standby Current <5µA
- Endurance, 100,000 Data Changes per Bit
- Register Data Retention, 100 years
- 8 Ld SOIC, PDIP, TSSOP, and MSOP
December 16, 2009
TOTAL
Recalled on Power-up
CC
All other trademarks mentioned are the property of their respective owners.
= 2.7V to 5.5V, and 5V ±10%
|
Values = 1kΩ, 10kΩ, 50kΩ, 100kΩ
Intersil (and design) is a registered trademark of Intersil Americas Inc.
X9317
FN8183.6

Related parts for X9317US8

X9317US8 Summary of contents

Page 1

... CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. | 1-888-INTERSIL or 1-888-468-3774 XDCP is a trademark of Intersil Americas, Inc. Copyright Intersil Americas Inc. 2004-2005, 2008, 2009. All Rights Reserved All other trademarks mentioned are the property of their respective owners. X9317 FN8183.6 ...

Page 2

... X9317UM8* (Note 2) AEC X9317UM8Z* (Note 1) DCS X9317UM8I* (Note 2) AFE X9317UM8IZ* (Note 1) DCR X9317UP (Note 2) X9317UP X9317UPI (Note 2) X9317UP I X9317US8* (Note 2) X9317U X9317US8Z* (Note 1) X9317U Z X9317US8I* (Note 2) X9317U I X9317US8IZ* (Note 1) X9317U ZI 2 X9317 V LIMITS R TEMPERATURE CC TOTAL (V) (kΩ) RANGE (°C) 5 ±10 + +70 -40 to +85 ...

Page 3

Ordering Information (Continued) PART NUMBER PART MARKING X9317UV8* (Note 2) 9317U X9317UV8Z* (Note 1) 9317U Z X9317UV8I* (Note 2) 317U I X9317UV8IZ* (Note 1) 9317U IZ X9317TM8*, ** (Note 2) AGD X9317TM8Z* (Note 1) DCN X9317TM8I*, ** (Note 2) AGF ...

Page 4

... X9317UM8Z-2.7* (Note 1) AOB X9317UM8I-2.7*, ** (Note 2) AFF X9317UM8IZ-2.7* (Note 1) AOH X9317US8-2.7* (Note 2) X9317U F X9317UP-2.7 (Note 2) X9317UP F X9317UPI-2.7 (Note 2) X9317UP G X9317US8Z-2.7* (Note 1) X9317U ZF X9317US8I-2.7*, ** (Note 2) X9317U G X9317US8IZ-2.7* (Note 1) X9317U ZG X9317UV8-2.7* (Note 2) 317U F X9317UV8Z-2.7* (Note 1) 9317U FZ X9317UV8I-2.7*, ** (Note 2) 317U G X9317UV8IZ-2.7* (Note 1) 9317U GZ X9317TM8-2.7*, ** (Note 2) AGE X9317TM8Z-2 ...

Page 5

Block Diagram V (SUPPLY VOLTAGE) CC UP/DOWN (U/D) CONTROL INCREMENT AND (INC) MEMORY DEVICE SELECT (CS) V (GROUND) SS GENERAL Pin Descriptions PDIP/SOIC/MSOP TSSOP SYMBOL 1 3 INC ...

Page 6

... CS, INC, U/D Input Capacitance IN 6 X9317 Thermal Information Junction Temperature Under Bias . . . . . . . . . . . . . .-65°C to +135°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp V = Full Range Full Operating Temperature Range, unless otherwise stated TEST CONDITIONS/NOTES See “Ordering Information” beginning on ...

Page 7

Endurance and Data Retention PARAMETER Minimum Endurance Data Retention NOTES: 1. Absolute linearity is utilized to determine actual wiper voltage versus expected voltage = [V(R V n(V(R )-V(R ))/99 + V(R W(n)(expected Relative linearity is ...

Page 8

Power-up and Down Requirements The recommended power-up sequence is to apply V first, then the potentiometer voltages. During power-up, the data sheet parameters for the DCP do not fully apply until AC Timing CS t CYC ...

Page 9

Pin Descriptions R AND The high (R ) and low (R ) terminals of the X9317 are H L equivalent to the fixed terminals of a mechanical potentiometer. The terminology relative position of the ...

Page 10

The system may select the X9317, move the wiper and deselect the device without having to store the latest wiper position in nonvolatile memory. After the wiper movement is performed as previously described and once the new position is reached, ...

Page 11

Basic Configurations of Electronic Potentiometers V REF THREE TERMINAL POTENTIOMETER; VARIABLE VOLTAGE DIVIDER Basic Circuits BUFFERED REFERENCE VOLTAGE +5V R LMC7101 REF - OUT W VOLTAGE REGULATOR V 317 IN R ...

Page 12

Mini Small Outline Plastic Packages (MSOP -B- INDEX 1 2 0.20 (0.008) AREA TOP VIEW 0.25 (0.010) GAUGE PLANE SEATING PLANE - 0.10 (0.004) b -H- - 0.20 (0.008) SIDE VIEW 0.20 ...

Page 13

Thin Shrink Small Outline Plastic Packages (TSSOP) N INDEX 0.25(0.010) E AREA E1 - 0.05(0.002) SEATING PLANE - -C- α 0.10(0.004) 0.10(0.004 NOTES: 1. These package ...

Page 14

Package Outline Drawing M8.15E 8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE Rev 0, 08/09 4 4.90 ± 0.10 PIN NO.1 ID MARK 5 1.27 TOP VIEW 1.75 MAX 0.175 ± 0.075 SIDE VIEW “A (1.27) (5.40) TYPICAL RECOMMENDED LAND ...

Page 15

... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use ...

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