X9252WV24-2.7 Intersil, X9252WV24-2.7 Datasheet - Page 9
![IC DCP QUAD 10K 256TAP 24-TSSOP](/photos/6/65/66570/20-24-tssop_sml.jpg)
X9252WV24-2.7
Manufacturer Part Number
X9252WV24-2.7
Description
IC DCP QUAD 10K 256TAP 24-TSSOP
Manufacturer
Intersil
Series
XDCP™r
Datasheet
1.X9252YV24IZ-2.7.pdf
(20 pages)
Specifications of X9252WV24-2.7
Taps
256
Resistance (ohms)
10K
Number Of Circuits
4
Temperature Coefficient
300 ppm/°C Typical
Memory Type
Non-Volatile
Interface
I²C, 2-Wire Serial
Voltage - Supply
2.7 V ~ 5.5 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
24-TSSOP
Resistance In Ohms
10K
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Up/Down Interface Operation
The SCL, U/D, CS, DS0 and DS1 inputs control the
movement of the wiper along the resistor array. With CS set
LOW the device is selected and enabled to respond to the
U/D and SCL inputs. HIGH to LOW transitions on SCL will
increment or decrement (depending on the state of the U/D
input) a wiper counter register selected by DS0 and DS1.
The output of this counter is decoded to select one of 256
wiper positions along the resistor array.
The value of the counter is stored in nonvolatile Data
Registers DRi0 whenever CS transitions HIGH while the
SCL and WP inputs are HIGH. “i” indicates the DCP number
selected with pins DS1 and DS0. During a “Store” operation
bits DRSel1 and DRSel0 in the Status Register must be both
“0”, which is their power up default value. Other
combinations are reserved and must not be used.
The system may select the X9252, move the wiper, and
deselect the device without having to store the latest wiper
position in nonvolatile memory. After the wiper movement is
performed as described above and once the new position is
reached, the system must keep SCL LOW while taking CS
HIGH. The new wiper position will be maintained until
changed by the system or until a power-down/up cycle
recalled the previously stored data.
This procedure allows the system to always power-up to a
preset value stored in nonvolatile memory; then during
system operation minor adjustments could be made. The
adjustments might be based on user preference, system
parameter changes due to temperate drift, etc.
The state of U/D may be changed while CS remains LOW.
This allows the host system to enable the device and then
move the wiper up and down until the proper trim is attained.
The 2-wire interface is disabled while CS remains LOW.
TABLE 1. DCP SELECTION FOR UP/DOWN CONTROL
DS1
0
0
1
1
DS0
0
1
0
1
9
SELECTED DCP
DCP0
DCP1
DCP2
DCP3
X9252
Mode Selection for Up/Down Control
2-Wire Serial Interface
Protocol Overview
The device supports a bidirectional bus oriented protocol.
The protocol defines any device that sends data onto the
bus as a transmitter, and the receiving device as the
receiver. The device controlling the transfer is called the
master and the device being controlled is called the slave.
The master always initiates data transfers, and provides the
clock for both transmit and receive operations. The X9252
operates as a slave in all applications.
All 2-wire interface operations must begin with a START,
followed by a Slave Address byte. The Slave Address
selects the X9252, and specifies if a Read or Write operation
is to be performed.
All Communication over the 2-wire interface is conducted by
sending the MSB of each byte of data first.
Serial Clock and Data
Data states on the SDA line can change only while SCL is
LOW. SDA state changes while SCL is HIGH are reserved
for indicating START and STOP conditions (See Figure 2).
On power up of the X9252, the SDA pin is in the input mode.
Serial Start Condition
All commands are preceded by the START condition, which
is a HIGH to LOW transition of SDA while SCL is HIGH. The
device continuously monitors the SDA and SCL lines for the
START condition and does not respond to any command
until this condition has been met (See Figure 2).
Serial Stop Condition
All communications must be terminated by a STOP
condition, which is a LOW to HIGH transition of SDA while
SCL is HIGH. The STOP condition is also used to place the
device into the Standby power mode after a read sequence.
A STOP condition can only be issued after the transmitting
device has released the bus (See Figure 2).
CS
H
L
L
SCL
H
X
L
L
L
U/D
H
H
L
X
X
X
L
Wiper Up
Wiper Down
Store Wiper Position to nonvolatile
memory if WP pin is high. No store,
return to standby, if WP pin is low.
Standby
No Store, Return to Standby
Wiper Up (not recommended)
Wiper Down
(not recommended)
MODE
November 14, 2005
FN8167.2