X95840WV20I-2.7T1 Intersil, X95840WV20I-2.7T1 Datasheet - Page 9

• Manufacturer Part Number: X95840WV20I-2.7T1
• Description: IC XDCP QUAD 256TAP 10K 20-TSSOP
• Manufacturer: Intersil
• Series: XDCP™r

Specifications of X95840WV20I-2.7T1

• Taps: 256
• Resistance (ohms): 10K
• Number Of Circuits: 4
• Temperature Coefficient: 45 ppm/°C Typical
• Memory Type: Non-Volatile
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-TSSOP
• Resistance In Ohms: 10K
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Typical Performance Curves
Principles of Operation
The X95840 in as integrated circuit incorporating four DCPs
with their associated registers, non-volatile memory, and a
I
a host and the potentiometers and memory.
DCP Description
Each DCP is implemented with a combination of resistor
elements and CMOS switches. The physical ends of each
DCP are equivalent to the fixed terminals of a mechanical
potentiometer (RH and RL pins). The RW pin of each DCP is
connected to intermediate nodes, and is equivalent to the
wiper terminal of a mechanical potentiometer. The position
of the wiper terminal within the DCP is controlled by an 8-bit
volatile Wiper Register (WR). Each DCP has its own WR.
When the WR of a DCP contains all zeroes (WR<7:0>: 00h),
its wiper terminal (RW) is closest to its “Low” terminal (RL).
When the WR of a DCP contains all ones (WR<7:0>: FFh),
its wiper terminal (RW) is closest to its “High” terminal (RH).
As the value of the WR increases from all zeroes (00h) to all
ones (255 decimal), the wiper moves monotonically from the
position closest to RL to the closest to RH. At the same time,
the resistance between RW and RL increases monotonically,
while the resistance between RH and RW decreases
monotonically.
While the X95840 is being powered up, all four WRs are
reset to 80h (128 decimal), which locates RW roughly at the
center between RL and RH. Soon after the power supply
voltage becomes large enough for reliable non-volatile
memory reading, the X95840 reads the value stored on four
different non-volatile Initial Value Registers (IVRs) and loads
them into their corresponding WRs.
The WRs and IVRs can be read or written directly using the
I
To access the general purpose bytes at addresses 4, 5, or 6,
FIGURE 13. MIDSCALE GLITCH, CODE 80h TO 7Fh (WIPER 0)
2
2
C serial interface providing direct communication between
C serial interface as described in the following sections.
Wiper Movement Mid Point
From 80h to 7fh
Signal at Wiper (Wiper Unloaded)
9
(Continued)
X95840
Memory Description
The X95840 contains eight non-volatile bytes. they are
accessed by I
through 7 decimal. The first four non-volatile bytes at
addresses 0, 1, 2, and 3, contain the initial value loaded at
power-up into the volatile Wiper Registers (WRs) of DCP0,
DCP1, DCP2, and DCP3 respectively. Bytes at addresses 4,
5, and 6 are available to the user as general purpose
registers. The byte at address 7 is reserved; the user should
not write to it, and its value should be ignored if read.
The volatile WR, and the non-volatile Initial Value Register
(IVR) of a DCP are accessed with the same Address Byte.
A volatile byte at address 8 decimal, controls what byte is
read or written when accessing DCP registers: the WR, the
IVR, or both.
When the byte at address 8 is all zeroes, which is the default
at power up:
• A read operation to addresses 0, 1, 2 or 3 outputs the
• A write operation to addresses 0, 1, 2, or 3 writes the
When the byte at address 8 is 80h (128 decimal):
• A read operation to addresses 0, 1, 2, or 3 outputs the
• A write operation to addresses 0, 1, 2, or 3 only writes to
It is not possible to write to an IVR without writing the same
value to its corresponding WR.
00h and 80h are the only values that should be written to
address 8. All other values are reserved and must not be
written to address 8.
the value at address 8 must be all zeros.
value of the non-volatile IVRs.
same value to the WR and IVR of the corresponding DCP.
value of the volatile WR.
the corresponding volatile WR.
FIGURE 14. LARGE SIGNAL SETTLING TIME
2
C interface operations with Address Bytes 0
SCL
Signal at Wiper
(Wiper Unloaded Movement
From ffh to 00h)
July 5, 2006
FN8213.2