MCP4921-E/SN Microchip Technology, MCP4921-E/SN Datasheet - Page 23

• Manufacturer Part Number: MCP4921-E/SN
• Description: IC DAC 12BIT SNGL W/SPI 8SOIC
• Manufacturer: Microchip Technology

Specifications of MCP4921-E/SN

• Number Of Converters: 1
• Package / Case: 8-SOIC (3.9mm Width)
• Settling Time: 4.5µs
• Number Of Bits: 12
• Data Interface: Serial, SPI™
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Resolution: 12 bit
• Interface Type: Serial (3-Wire, SPI, Microwire)
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.7 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Package: 8SOIC N
• Architecture: Resistor-String
• Digital Interface Type: Serial (3-Wire, SPI, Microwire)
• Number Of Outputs Per Chip: 1
• Output Type: Voltage
• Full Scale Error: 1 %FSR
• Integral Nonlinearity Error: ±12 LSB
• Maximum Settling Time: 4.5(Typ) us
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power Dissipation (max): -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

5.0
5.1
The MCP4901/4911/4921 devices are designed to
interface directly with the Serial Peripheral Interface
(SPI) port, which is available on many microcontrollers
and supports Mode 0,0 and Mode 1,1. Commands and
data are sent to the device via the SDI pin, with data
being clocked-in on the rising edge of SCK. The
communications are unidirectional, thus the data
cannot be read out of the MCP4901/4911/4921. The
CS pin must be held low for the duration of a write
command. The write command consists of 16 bits and
is used to configure the DAC’s control and data latches.
Register 5-1 through Register 5-3 detail the input regis-
ter that is used to configure and load the DAC register
for each device.
the write command for each device.
Refer to
Table for detailed input and output timing specifications
for both Mode 0,0 and Mode 1,1 operation.
 2010 Microchip Technology Inc.
Figure 1-1
SERIAL INTERFACE
Overview
Figure 5-1
and the SPI Timing Specifications
through
Figure 5-3
show
5.2
The write command is initiated by driving the CS pin
low, followed by clocking the four Configuration bits and
the 12 data bits into the SDI pin on the rising edge of
SCK. The CS pin is then raised, causing the data to be
latched into the DAC’s input register.
The MCP4901/4911/4921 utilizes a double-buffered
latch structure to allow the analog output to be
synchronized with the LDAC pin, if desired.
By bringing the LDAC pin down to a low state, the con-
tent stored in the DAC’s input register is transferred into
the DAC’s output register (V
All writes to the MCP4901/4911/4921 devices are
16-bit words. Any clocks past the 16th clock will be
ignored. The Most Significant 4 bits are Configuration
bits. The remaining 12 bits are data bits. No data can
be transferred into the device with CS high. This
transfer will only occur if 16 clocks have been
transferred into the device. If the rising edge of CS
occurs prior to that, shifting of data into the input
register will be aborted.
MCP4901/4911/4921
Write Command
OUT
), and V
DS22248A-page 23
OUT
is updated.