CS4392-KZZ Cirrus Logic Inc, CS4392-KZZ Datasheet

IC DAC 24BIT 192KHZ W/VC 20TSSOP

CS4392-KZZ

Manufacturer Part Number
CS4392-KZZ
Description
IC DAC 24BIT 192KHZ W/VC 20TSSOP
Manufacturer
Cirrus Logic Inc
Datasheet

Specifications of CS4392-KZZ

Package / Case
20-TSSOP
Number Of Bits
24
Data Interface
Serial
Number Of Converters
2
Voltage Supply Source
Analog and Digital
Power Dissipation (max)
150mW
Operating Temperature
-10°C ~ 70°C
Mounting Type
Surface Mount
Conversion Rate
200 KSPS
Resolution
24 bit
Interface Type
Serial
Operating Supply Voltage
5 V
Operating Temperature Range
+ 70 C
Maximum Power Dissipation
150 mW
Mounting Style
SMD/SMT
Number Of Dac Outputs
2
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
CDB4392 - EVALUATION BOARD FOR CS4392
Settling Time
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
598-1065-5

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CS4392-KZZ
Manufacturer:
CIRRUS
Quantity:
20 000
Company:
Part Number:
CS4392-KZZ
Quantity:
999
Part Number:
CS4392-KZZR
Manufacturer:
CIRRUS
Quantity:
20 000
Features
Preliminary Product Information
http://www.cirrus.com
Complete Stereo DAC System: Interpolation,
D/A, Output Analog Filtering
114 dB Dynamic Range
100 dB THD+N
Up to 192kHz Sample Rates
Direct Stream Digital Mode
Low Clock Jitter Sensitivity
Single +5 V Power Supply
Selectable Digital Filters
– Fast and Slow roll-off
Volume Control with Soft Ramp
– 1 dB Step Size
– Zero Crossing Click-Free Transitions
Direct Interface with 5 V to 1.8 V Logic
ATAPI Mixing Functions
Pin Compatible with the CS4391
I
24-Bit, 192 kHz Stereo DAC with Volume Control
SDATA
SCLK
LRCK
RST
SERIAL
(SDA/CDIN)
PORT
M1
(CONTROL PORT)
MODE SELECT
M3
CONTROL
CONTROL
VOLUME
VOLUME
MIXER
(SCL/CCLK)
Copyright © Cirrus Logic, Inc. 2002
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
M2
(All Rights Reserved)
(AD0/CS)
M0
INTERPOLATION
INTERPOLATION
FILTER
FILTER
Description
The CS4392 is a complete stereo digital-to-analog sys-
tem including digital interpolation, fifth-order delta-sigma
digital-to-analog conversion, digital de-emphasis, vol-
ume control, channel mixing and analog filtering. The
advantages of this architecture include: ideal differential
linearity, no distortion mechanisms due to resistor
matching errors, no linearity drift over time and tempera-
ture, and a high tolerance to clock jitter.
The CS4392 accepts PCM data at sample rates from
4 kHz to 192 kHz, DSD audio data, has selectable digital
filters, and consumes very little power. These features
are ideal for DVD, SACD players, A/V receivers, CD and
set-top box systems. The CS4392 is pin and register
compatible with the CS4391, making easy performance
upgrades possible.
ORDERING INFORMATION
CS4392-KS
CS4392-KZ
CS4392-KZZ, Lead Free -10 to 70 °C 20-pin TSSOP
CDB4392
AMUTEC
MUTE CONTROL
EXTERNAL
MCLK
BMUTEC
DAC
DAC
∆Σ
∆Σ
CMOUT
REFERENCE
ANALOG
ANALOG
FILTER
FILTER
FILT+
-10 to 70 °C 20-pin SOIC
-10 to 70 °C 20-pin TSSOP
AOUTA+
AOUTA-
AOUTB+
AOUTB-
CS4392
Evaluation Board
DS459PP3
SEP ‘04

Related parts for CS4392-KZZ

CS4392-KZZ Summary of contents

Page 1

... These features are ideal for DVD, SACD players, A/V receivers, CD and set-top box systems. The CS4392 is pin and register compatible with the CS4391, making easy performance upgrades possible. ORDERING INFORMATION CS4392-KS CS4392-KZ CS4392-KZZ, Lead Free - °C 20-pin TSSOP CDB4392 (SCL/CCLK) (AD0/CS) ...

Page 2

... SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trade- marks or service marks of their respective owners. 2 CS4392 DS459PP3 ...

Page 3

... Interpolation Filter Select (Bit 4) .............................................................23 6.6.2 Soft Volume Ramp-up after Reset (Bit 3) ..............................................24 6.6.3 Soft Ramp-down before Reset (Bit 2) ....................................................24 6.7 Chip ID - Register 07h .....................................................................................24 7. CHARACTERISTICS/SPECIFICATIONS ..................................................................25 ANALOG CHARACTERISTICS (CS4392-KS/KZ/KZZ)...........................................25 COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE ............................................................................................................26 SWITCHING CHARACTERISTICS - SERIAL AUDIO INTERFACE .......................32 SWITCHING SPECIFICATIONS - DSD INTERFACE.............................................33 SWITCHING CHARACTERISTICS - CONTROL PORT INTERFACE ...

Page 4

... LIST OF FIGURES Figure 1. Typical Connection Diagram - PCM Mode....................................................................... 7 Figure 2. Typical Connection Diagram - DSD Mode ....................................................................... 8 Figure 3. CS4392 Output Filter ....................................................................................................... 9 Figure 4. Format 0, Left Justified up to 24-Bit Data....................................................................... 11 Figure 5. Format 1, I2S up to 24-Bit Data ..................................................................................... 11 Figure 6. Format 2, Right Justified 16-Bit Data Format 3, Right Justified 24-Bit Data Format 4, Right Justified 20-Bit Data ...

Page 5

... M0 DS459PP3 1 20 RST AMUTEC AOUTA SDATA AOUTA SCLK LRCK AGND 6 15 MCLK AOUTB AOUTB BMUTEC 9 12 CMOUT 10 11 FILT Control Port Chip Select (SPI) (Input/Output) - AD0 is a chip address pin in I CS4392 2 C mode. CDIN is the input data line for ...

Page 6

... DSD Mode (Input stand alone mode, this pin must be set to a logic ‘1’ for operation of DSD Mode. DSD_SCLK 7 DSD Serial Clock (Input/Output) - Serial clock for the Direct Stream Digital audio interface RST 20 AMUTEC AOUTA DSD_A AOUTA DSD_B AGND 6 15 MCLK AOUTB AOUTB BMUTEC 9 12 CMOUT 10 11 FILT+ CS4392 DS459PP3 ...

Page 7

... A high logic level for all digital inputs should not exceed VL. DS459PP3 0.1 µ (AD0/CS (SDA/CDIN) FILT (SCL/CCLK CS4392 2 AOUTA- VL AMUTEC 20 5 AOUTA+ LRCK 4 SCLK AOUTB- 3 SDATA BMUTEC 13 1 RST AOUTB+ 6 MCLK CMOUT AGND 16 CS4392 +5V Analog µ 0.1 µf 10 µ Analog Conditioning & 18 Mute 14 Analog Conditioning & 15 Mute 12 1.0 µ ...

Page 8

... M0 (AD0/CS) FILT (SDA/ CDIN (SCL/CCLK) CS4392 AOUTA AMUTEC 5 DSD_MODE AOUTA+ 7 DSD_CLK 4 DSD_B AOUTB- 3 DSD_A BMUTEC 1 RST AOUTB+ 6 MCLK CMOUT AGND 16 CS4392 +5V Analog µ + 1.0 f 0.1 µf 11 0.1 µf 10 µ Analog 20 Conditioning & 18 Mute 14 Analog Conditioning 13 & 15 Mute 12 1.0 µf + DS459PP3 ...

Page 9

... The circuit in figure 3 may also be DC coupled, however the filter on the CDB4392 must be AC coupled. The CS4392 is a linear phase design and does not include phase or amplitude compensation for an external filter. Therefore, the DAC system phase and amplitude response will be dependent on the external analog circuitry ...

Page 10

... Interpolation Filter To accommodate the increasingly complex requirements of digital audio systems, the CS4392 incorpo- rates selectable interpolation filters for each mode of operation. A fast and a slow roll-off filter is available in each of Single, Double, and Quad Speed modes. These filters have been designed to accommodate a variety of musical tastes and styles ...

Page 11

... Format 4, Right Justified 20-Bit Data. (Available in Control Port Mode only) Format 5, Right Justified 18-Bit Data. (Available in Control Port Mode only) DS459PP3 DESCRIPTION + Figure 4. Format 0, Left Justified up to 24-Bit Data + LSB MSB - Figure 5. Format 24-Bit Data + Format 3, Right Justified 24-Bit Data CS4392 FORMAT FIGURE nel + LSB ...

Page 12

... Oversampling Modes The CS4392 operates in one of three oversampling modes based on the input sample rate. Mode selection is determined by the M3 and M2 pins in Stand-Alone mode or the FM bits in Control Port mode. Single- Speed mode supports input sample rates kHz and uses a 128x oversampling ratio. Double-Speed mode supports input sample rates up to 100 kHz and uses an oversampling ratio of 64x ...

Page 13

... DSD data with a 2x MCLK to DSD data rate 0 128x oversampled DSD data with a 3x MCLK to DSD data rate 1 128x oversampled DSD data with a 4x MCLK to DSD data rate 0 128x oversampled DSD data with a 6x MCLK to DSD data rate 1 CS4392 DESCRIPTION 13 ...

Page 14

... START condition and follow the procedure detailed from step further writes to other registers are desired, initiate a STOP condition to the bus communication bus followed by the address byte. The upper 6 bits 2 C writes to other registers are desired nec- CS4392 2 C writes DS459PP3 ...

Page 15

... eration rite , th is byte con the dress P o inter DS459PP3 2 C bus followed by the address byte. The upper 6 bits 2 C reads from other registers are desired nec- N ote Figure 8. Control Port Timing Mode CS4392 2 C read is the first 2 C Read section further 1-8 Stop 15 ...

Page 16

... MAP will auto increment after each byte is written, allowing block reads Enabled, writes of successive registers 4.1.2 MAP3-0 (MEMORY ADDRESS POINTER) Default = ‘0000’ ADDRESS MSB R/W byte ory Ad dress P oin te r Figure 9. Control Port Timing, SPI mode Reserved MAP3 CS4392 DATA byte MAP2 MAP1 MAP0 0 0 DS459PP3 0 0 ...

Page 17

... Zero Soft ATAPI4 Cross VOL6 VOL5 VOL4 VOL6 VOL5 VOL4 CPEN PDN MUTEC Reserved Reserved FILT_SEL PART2 PART1 PART0 CS4392 DEM1 DEM0 FM1 ATAPI3 ATAPI2 ATAPI1 VOL3 VOL2 VOL1 VOL3 VOL2 VOL1 FREEZE MCLKDIV2 Reserved RMP_UP RMP_DN Reserved Reserved REV3 ...

Page 18

... Table 8. Digital Interface Formats - PCM Modes DIF1 DIF0 DEM1 DESCRIPTION Left Justified 24-bit data (default 24-bit data Right Justified, 16-bit Data Right Justified, 24-bit Data Right Justified, 20-bit Data Right Justified, 18-bit Data Reserved Reserved CS4392 DEM0 FM1 FM0 Format Figure ...

Page 19

... DSD data with a 3x MCLK to DSD data rate 128x oversampled DSD data with a 4x MCLK to DSD data rate 128x oversampled DSD data with a 6x MCLK to DSD data rate Table 9. Digital Interface Formats - DSD Mode Gain dB 0dB -10dB MODE CS4392 DESCRIPTION T1=50 µ µ Frequency 3.183 kHz 10.61 kHz Figure 10 ...

Page 20

... Soft Ramp enabled (default Soft Ramp and Zero Cross enabled Table 12. Soft Cross or Zero Cross Mode Selection 6.2.3 ATAPI Channel Mixing and Muting (Bits 4:0) Function: The CS4392 implements the channel mixing functions of the ATAPI CD-ROM specification. See Table 13 on page ATAPI4 ATAPI3 ...

Page 21

... MUTE [(aL+bR)/ [(aL+bR)/ [(bL+aR)/ [(aL+bR)/2] Table 13. ATAPI Decode A Channel Volume Control Σ B Channel Volume Control Figure 11. ATAPI Block Diagram CS4392 AOUTB MUTE bR bL b[(L+R)/2] aR MUTE b[(L+R)/2] aL MUTE b[(L+R)/2] MUTE bR bL b[(L+R)/2] MUTE bR bL [(bL+aR)/2] aR MUTE [(aL+bR)/2] aL MUTE ...

Page 22

... When set to 1, this bit inverts the signal polarity for the appropriate channel. This is useful if a board layout error has occurred other situations where a 180 degree phase shift is desirable. Default VOL4 VOL3 Volume Setting -20 dB -40 dB - PDN MUTEC CS4392 VOL2 VOL1 VOL0 FREEZE MCLKDIV2 Reserved DS459PP3 ...

Page 23

... This Function allows the user to select whether the Interpolation Filter has a fast (set default) or slow (set to 1) roll off. The - 3dB corner is approximately the same for both filters, but the slope of the roll of is greater for the ‘fast’ roll off filter. DS459PP3 FILT_SEL RMP_UP CS4392 RMP_DN Reserved Reserved 23 ...

Page 24

... Chip ID - Register 07h B7 B6 PART3 PART2 PART1 Function: This register is Read-Only. Bits 7 through 4 are the part number ID which is 1000b (8h) and the re- maining Bits (3 through 0) are for the chip revision PART0 REV3 CS4392 REV2 REV1 REV0 DS459PP3 ...

Page 25

... CHARACTERISTICS/SPECIFICATIONS ANALOG CHARACTERISTICS (CS4392-KS/KZ/KZZ) specified): Input test signal is a 997 Hz sine wave at 0 dBFS; measurement bandwidth kHz; test load R = 3kΩ pF. Typical performance characteristics are derived from measurements taken 5.0V. Min/Max performance characteristics are guaranteed over the specified operating temperature and voltages.) ...

Page 26

... kHz - Fs = 44.1 kHz - kHz - to -0.01 dB corner corner 0 -0.01 0.583 80 (Note kHz - to -0.01 dB corner corner 0 -0.01 0.635 90 (Note kHz - to -0.1 dB corner corner 0 -.01 CS4392 (The Typ Max Unit - 0.454 Fs - 0.499 Fs - +0. 12/ ±0.41/ ±0. ±0. ±0. 0.430 Fs - 0.499 Fs - ...

Page 27

... kHz - Fs = 44.1 kHz - kHz - to -0.01 dB corner corner 0 -0.01 0.792 70 (Note kHz to -0.01 dB corner corner 0 -0.01 0.868 75 (Note kHz to -0.1 dB corner corner 0 -.01 CS4392 (Cont.) (Note 3) Typ Max Unit - 0.417 Fs - 0.499 Fs - +0. 6.5/ ±0.14/ ±0. ±0. ±0. 0.296 ...

Page 28

... Figure 15. Single Speed (fast) Passband Ripple 100 120 0.8 0.9 1 0.4 0.42 Figure 17. Single Speed (slow) Transition Band CS4392 0.44 0.46 0.48 0.5 0.52 0.54 0.56 0.58 Frequency(normalized to Fs) 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 Frequency(normalized to Fs) ...

Page 29

... Figure 21. Double Speed (fast) Transition Band 0.02 0.015 0.01 0.005 0 0.005 0.01 0.015 0.02 0.52 0.53 0.54 0.55 0 0.05 Figure 23. Double Speed (fast) Passband Ripple CS4392 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 Frequency(normalized to Fs) 0.44 0.46 0.48 0.5 0.52 0.54 0.56 ...

Page 30

... Figure 27. Double Speed (slow) Passband Ripple 100 120 0.2 0.7 0.8 0.9 1 Figure 29. Quad Speed (fast) Transition Band CS4392 0.3 0.4 0.5 0.6 0.7 Frequency(normalized to Fs) 0.05 0.1 0.15 0.2 0.25 0.3 Frequency(normalized to Fs) 0.3 0.4 0.5 0.6 ...

Page 31

... Figure 33. Quad Speed (slow) Transition Band 0.02 0.015 0.01 0.005 0 0.005 0.01 0.015 0.02 0 0.52 0.53 0.54 0.55 Figure 35. Quad Speed (slow) Passband Ripple CS4392 0.05 0.1 0.15 0.2 Frequency(normalized to Fs) 0.3 0.4 0.5 0.6 0.7 0.8 Frequency(normalized to Fs) 0.02 0.04 0.06 ...

Page 32

... SDATA valid to SCLK rising setup time SCLK rising to SDATA hold time ATA 32 Symbol Fs Single Speed Mode Double Speed Mode t slrd t slrs t sdlrs t sdh t slrs t slrd t sdlrs Figure 36. Serial Mode Input Timing CS4392 Min Typ Max 4 - 200 128•LRCK - - 64•LRCK - - MCLK MCLK/4 ...

Page 33

... DSD_L or DSD_R valid to DSD_SCLK rising setup time DSD_SCLK rising to DSD_L or DSD_R hold time SD_L, DSD_R Figure 37. Direct Stream Digital - Serial Audio Input Timing DS459PP3 (Logic 0 = AGND; Logic 1 = VL) Symbol Min sclkl t 20 sclkh 20 t sclkw t 20 sdlrs t 20 sdh t sclkh t sclkl t t sdlrs sdh CS4392 Max Unit ...

Page 34

... high t hdst sud lo w hdd 2 Figure 38 Mode Control Port Timing Min Max - 100 scl 500 - irs 4.7 - 4.0 - 4.7 - 4 250 - 300 f 4.7 - Stop susp hdst t sust t r CS4392 Unit kHz ns µs µs µs µs µs µs ns µs ns µs DS459PP3 ...

Page 35

... DS459PP3 Symbol f sclk t srs (Note 7) t spi t csh t css t scl t sch t dsu (Note (Note (Note srs t spi t css t scl t sch Figure 39. SPI Control Port Timing CS4392 (Inputs: logic 0 = AGND, Min Max Unit - 6 MHz 500 - ns 500 - ns 1.0 - µ 100 ns - 100 all other times. ...

Page 36

... Ambient Operating Temperature 36 (AGND = 0V; all voltages with respect to AGND.) Symbol Min All Supplies=5. All Supplies=5. kHz) PSRR (60 Hz) CMOUT Symbol Min 70 Symbol Min θ CS4392-KS JA θ CS4392-KZ/KZZ JA (Power Applied) T -10 A CS4392 Typ Max Units - 130 150 mW µA - 300 - - 1 0.48• 250 - kΩ - 0.001 - ...

Page 37

... DS459PP3 (AGND = 0V; all voltages with respect Symbol Min VA 4.75 VL 1.8 (AGND = 0 V; all voltages with respect to ground.) Symbol Min VA -0 -0.3 IND T - -65 stg CS4392 Typ Max Units 5.0 5. Max Units 6 ±10 mA VL+0.4 V 125 °C 150 °C 37 ...

Page 38

... The deviation from the nominal full scale analog output for a full scale digital input. Gain Drift The change in gain value with temperature. Units in ppm/°C. 9. REFERENCES 1. CDB4392 Evaluation Board Datasheet 2 2. “The I C-Bus Specification: Version 2.1” Philips Semiconductors, January 2000. http://www.semiconductors.philips.com 38 CS4392 DS459PP3 ...

Page 39

... JEDEC #: MO-153 Controlling Dimension is Millimeters END VIEW L MILLIMETERS NOM MAX -- -- 1.10 -- 0.15 0.90 0.95 0.245 0.30 6.50 6.60 6.40 6.50 4.40 4. 0.65 0.60 0.70 4° 8° CS4392 ∝ NOT E 2 ...

Page 40

... JEDEC #: MS-013 Controlling Dimension is Millimeters CS4392 MILLIMETERS MIN NOM MAX 2.35 2.50 2.65 0.10 0.20 0.30 0.33 0.43 0.51 0.23 0.28 ...

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