AD9761ARSZ Analog Devices Inc, AD9761ARSZ Datasheet
AD9761ARSZ
Specifications of AD9761ARSZ
Available stocks
Related parts for AD9761ARSZ
AD9761ARSZ Summary of contents
Page 1
FEATURES Complete 10-Bit, 40 MSPS Dual Transmit DAC Excellent Gain and Offset Matching Differential Nonlinearity Error: 0.5 LSB Effective Number of Bits: 9.5 Signal-to-Noise and Distortion Ratio Spurious-Free Dynamic Range 2 Interpolation Filters 20 MSPS/Channel Data ...
Page 2
AD9761–SPECIFICATIONS DC SPECIFICATIONS ( MIN Parameter RESOLUTION DC ACCURACY 1 Integral Nonlinearity Error (INL 25° MIN MAX Differential Nonlinearity (DNL 25° MIN MAX Monotonicity (10-Bit) ANALOG ...
Page 3
DYNAMIC SPECIFICATIONS Parameter DYNAMIC PERFORMANCE Maximum Output Update Rate Output Settling Time (t to 0.025%) ST Output Propagation Delay ( Glitch Impulse Output Rise Time (10% to 90%) Output Fall Time (10% to 90%) AC LINEARITY TO NYQUIST ...
Page 4
AD9761 DIGITAL FILTER SPECIFICATIONS Parameter MAXIMUM INPUT CLOCK RATE (f DIGITAL FILTER CHARACTERISTICS 1 Pass Bandwidth : 0.005 dB Pass Bandwidth: 0.01 dB Pass Bandwidth: 0.1 dB Pass Bandwidth: –3 dB Linear Phase (FIR Implementation) Stop-Band Rejection: 0 ...
Page 5
ORDERING GUIDE Package Model Description AD9761ARS 28-Lead Shrink Small Outline (SSOP) RS-28 AD9761ARSRL 28-Lead Shrink Small Outline (SSOP) RS-28 AD9761-EB Evaluation Board ABSOLUTE MAXIMUM RATINGS* Parameter AVDD DVDD ACOM AVDD CLOCK, WRITE SELECT, SLEEP Digital Inputs IOUTA, IOUTB QOUTA, QOUTB ...
Page 6
AD9761 Pin No. Mnemonic Description 1 DB9 Most Significant Data Bit (MSB). 2–9 DB8–DB1 Data Bits 1–8. 10 DB0 Least Significant Data Bit (LSB). 11 CLOCK Clock Input. Both DACs’ outputs updated on positive edge of clock and digital filters ...
Page 7
DEFINITIONS OF SPECIFICATIONS Linearity Error (Also Called Integral Nonlinearity or INL) Linearity error is defined as the maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from zero to full scale. Differential ...
Page 8
AD9761—Typical Performance Characteristics Typical AC Characterization Curves @ 5 V Supplies (AVDD = 5 V, DVDD = Doubly Terminated Load, T performance shown.) 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 START: 0Hz ...
Page 9
Typical AC Characterization Curves @ 3 V Supplies (AVDD = 3 V, DVDD = Doubly Terminated Load, T performance shown.) 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 START: 0Hz STOP: 10MHz TPC 10. ...
Page 10
AD9761 FUNCTIONAL DESCRIPTION Figure 4 shows a simplified block diagram of the AD9761. The AD9761 is a complete dual-channel, high speed, 10-bit CMOS DAC capable of operating MHz clock rate. It has been optimized for the ...
Page 11
Referring to Figure 5, the “new” first image associated with the DAC’s higher data rate after interpolation ...
Page 12
AD9761 REFLO AVDD +1.2V REF EXT. REFIO V REF FSADJ R SET I = REF V /R REF SET AD9761 Figure 7. External Reference Configuration REFERENCE CONTROL AMPLIFIER The AD9761 also contains an internal control amplifier that is used to ...
Page 13
The positive output compliance range is slightly dependent on the full-scale output current degrades slightly from OUTFS its nominal 1.25 V for 1.00 V for an OUTFS mA. ...
Page 14
AD9761 result, the digital inputs can also accommodate TTL levels when DVDD is set to accommodate the maximum high level voltage the TTL drivers. A DVDD OH(MAX) to 3.3 V will typically ensure proper ...
Page 15
RATIO (f /f OUT CLK Figure 16. I vs. Ratio @ DVDD = 3 V DVDD APPLYING THE AD9761 Output Configurations The following sections ...
Page 16
AD9761 The differential circuit shown in Figure 19 provides the neces- sary level-shifting required in a single-supply system. In this case, AVDD, which is the positive analog supply for both the AD9761 and the op amp, is also used to ...
Page 17
Maintaining low noise on power supplies and ground is critical to obtaining optimum results from the AD9761. If properly implemented, ground planes can perform a host of functions on high speed circuit boards such as bypassing, shielding, current transport. In ...
Page 18
AD9761 Figure 24a. Evaluation Board Schematic –18– REV. C ...
Page 19
REV. C Figure 24b. Evaluation Board Schematic –19– AD9761 ...
Page 20
AD9761 Figure 25. Silkscreen Layer—Top Figure 26. Component Side PCB Layout (Layer 1) –20– REV. C ...
Page 21
REV. C Figure 27. Ground Plane PCB Layout (Layer 2) Figure 28. Power Plane PCB Layout (Layer 3) –21– AD9761 ...
Page 22
AD9761 Figure 29. Solder Side PCB Layout (Layer 4) Figure 30. Silkscreen Layer—Bottom –22– REV. C ...
Page 23
MAX 0.05 MIN REV. C OUTLINE DIMENSIONS 28-Lead Shrink Small Outline Package [SSOP] (RS-28) Dimensions shown in millimeters 10.50 10.20 9. 5.60 8.20 5.30 7.80 5.00 7. 1.85 1.75 0.10 1.65 COPLANARITY 0.25 0.09 0.65 ...
Page 24
AD9761 Revision History Location 6/03—Data Sheet changed from REV REV. C. Renumbered TPCs and subsequent figures . . . . . . . . . . . . . . . . . . . . . . ...