DAC104S085CISD/NOPB National Semiconductor, DAC104S085CISD/NOPB Datasheet - Page 15

IC DAC 10BIT QUAD 10-LLP

DAC104S085CISD/NOPB

Manufacturer Part Number
DAC104S085CISD/NOPB
Description
IC DAC 10BIT QUAD 10-LLP
Manufacturer
National Semiconductor
Series
PowerWise®r
Datasheet

Specifications of DAC104S085CISD/NOPB

Settling Time
4.5µs
Number Of Bits
10
Data Interface
Serial
Number Of Converters
4
Voltage Supply Source
Single Supply
Power Dissipation (max)
2.5mW
Operating Temperature
-40°C ~ 105°C
Mounting Type
Surface Mount
Package / Case
10-LLP
For Use With
DAC104S085EB - BOARD EVALUATION DAC104S085
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
DAC104S085CISDTR
Normally, the SYNC line is kept low for at least 16 falling
edges of SCLK and the DAC is updated on the 16th SCLK
falling edge. However, if SYNC is brought high before the 16th
falling edge, the data transfer to the shift register is aborted
and the write sequence is invalid. Under this condition, the
DAC register is not updated and there is no change in the
mode of operation or in the DAC output voltages.
1.6 POWER-ON RESET
The power-on reset circuit controls the output voltages of the
four DACs during power-up. Upon application of power, the
DAC registers are filled with zeros and the output voltages are
0V. The outputs remain at 0V until a valid write sequence is
made to the DAC.
1.7 POWER-DOWN MODES
The DAC104S085 has four power-down modes, two of which
are identical. In power-down mode, the supply current drops
to 20 µA at 3V and 30 µA at 5V. The DAC104S085 is set in
power-down mode by setting OP1 and OP0 to 11. Since this
mode powers down all four DACs, the address bits, A1 and
A0, are used to select different output terminations for the
DAC outputs. Setting A1 and A0 to 00 or 11 causes the out-
puts to be tri-stated (a high impedance state). While setting
A1 and A0 to 01 or 10 causes the outputs to be terminated by
2.5 kΩ or 100 kΩ to ground respectively (see Table 1).
The bias generator, output amplifiers, resistor strings, and
other linear circuitry are all shut down in any of the power-
A1
0
0
1
1
A0
0
1
0
1
TABLE 1. Power-Down Modes
OP1
1
1
1
1
OP0
1
1
1
1
 Operating Mode
100 kΩ to GND
High-Z outputs
2.5 kΩ to GND
High-Z outputs
FIGURE 4. Input Register Contents
15
down modes. However, the contents of the DAC registers are
unaffected when in power-down. Each DAC register main-
tains its value prior to the DAC104S085 being powered down
unless it is changed during the write sequence which instruct-
ed it to recover from power down. Minimum power consump-
tion is achieved in the power-down mode with SYNC and
D
(Wake-Up Time) is typically t
Timing Characteristics table.
2.0 Applications Information
2.1 USING REFERENCES AS POWER SUPPLIES
While the simplicity of the DAC104S085 implies ease of use,
it is important to recognize that the path from the reference
input (V
Supply Rejection Ratio (PSRR). Therefore, it is necessary to
provide a noise-free supply voltage to V
lize the full dynamic range of the DAC104S085, the supply
pin (V
same supply voltage. Since the DAC104S085 consumes very
little power, a reference source may be used as the reference
input and/or the supply voltage. The advantages of using a
reference source over a voltage regulator are accuracy and
stability. Some low noise regulators can also be used. Listed
below are a few reference and power supply options for the
DAC104S085.
2.1.1 LM4130
The LM4130, with its 0.05% accuracy over temperature, is a
good choice as a reference source for the DAC104S085. The
4.096V version is useful if a 0 to 4.095V output range is de-
sirable or acceptable. Bypassing the LM4130 VIN pin with a
0.1µF capacitor and the VOUT pin with a 2.2µF capacitor will
improve stability and reduce output noise. The LM4130
comes in a space-saving 5-pin SOT23.
IN
idled low and SCLK disabled. The time to exit power-down
A
) and V
REFIN
) to the VOUTs will have essentially zero Power
REFIN
can be connected together and share the
20195308
WU
µsec as stated in the A.C. and
REFIN
. In order to uti-
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