MAX5556ESA+ Maxim Integrated Products, MAX5556ESA+ Datasheet - Page 12

• Manufacturer Part Number: MAX5556ESA+
• Description: IC DAC STEREO AUDIO 8-SOIC
• Manufacturer: Maxim Integrated Products

Specifications of MAX5556ESA+

• Number Of Bits: 16
• Data Interface: Serial
• Number Of Converters: 2
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Number Of Dac Outputs: 2
• Resolution: 16 bit
• Interface Type: Serial (3-Wire)
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4.75 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Maximum Power Dissipation: 471 mW
• Minimum Operating Temperature: - 40 C
• Supply Current: 13 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power Dissipation (max): -
• Settling Time: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

LRCLK is the left/right clock input signal for the 3-wire
interface and sets the sample frequency (f
MAX5556, drive LRCLK low to direct data to OUTL or
LRCLK high to direct data to OUTR (Figure 4). On the
MAX5557/MAX5558/MAX5559, drive LRCLK high to
direct data to OUTL or LRCLK low to direct data to
OUTR (Figures 5, 6, 7). LRCLK is internally resampled
on each SCLK rising edge. The MAX5556–MAX5559
accept data at LRCLK audio sample rates from 2kHz to
50kHz.
MCLK accepts the master clock signal from an external
clocking device and is used to derive internal clock fre-
quencies. Set the MCLK/LRCLK ratio to 256, 384, or
512 to achieve the internal serial clock frequencies list-
ed in Table 1. Table 2 details the MCLK/LRCLK ratios
for three sample audio rates.
The MAX5556–MAX5559 detect the MCLK/LRCLK ratio
during the initialization sequence by counting the num-
ber of MCLK transitions during a single LRCLK period.
MCLK, SCLK, and LRCLK must be synchronous sig-
nals.
Low-Cost Stereo Audio DACs
Table 1. Internal and External Clock
Frequencies
Table 2. MCLK/LRCLK Ratios
12
LRCLK
MAX5556
MAX5557
MAX5558
MAX5559
(kHz)
44.1
PART
32
48
_______________________________________________________________________________________
MCLK/LRCLK
M C L K /L R C L K
11.2896
12.2880
= 2 5 6 O R 51 2
8.1920
= 256
32 x f
64 x f
32 x f
64 x f
CLOCK FREQUENCY
INTERNAL SERIAL
S
S
S
S
Left/Right Clock Input (LRCLK)
MCLK/LRCLK
MCLK (MHz)
M C L K /L R C L K
12.2880
16.9344
18.4320
= 384
48 x f
48 x f
48 x f
48 x f
= 3 8 4
Master Clock (MCLK)
S
S
S
S
MCLK/LRCLK
FREQUENCY
User defined
User defined
User defined
User defined
EXTERNAL
(Figure 4)
(Figure 5)
(Figure 6)
(Figure 7)
16.3840
22.5792
24.5760
S
SERIAL
CLOCK
= 512
). On the
The MAX5556 accepts data with an I
data format, accepting up to 24 bits of data. SDATA
accepts data in two’s complement format with the MSB
first. The MSB is valid on the second SCLK rising edge
after LRCLK transitions low to high or high to low
(Figure 4). Drive LRCLK low to direct data to OUTL.
Drive LRCLK high to direct data to OUTR. The number
of SCLK pulses with LRCLK high or low determines the
number of bits transferred per sample. If fewer than 24
bits of data are written, the remaining LSBs are set to 0.
If more than 24 bits are written, any bits after the LSB
are ignored.
The MAX5556 accepts up to 24 bits of data in external
serial clock mode or when the MCLK/LRCLK ratio is
384 (internal serial clock = 48 x f
clock mode. The DAC also accepts 16 bits of data in
internal serial clock mode when the MCLK/LRCLK ratio
is 256 or 512 (internal serial clock = 32 x f
The MAX5557 accepts data with a left-justified data for-
mat, allowing for up to 24 bits of data. SDATA accepts
data in two’s complement format with the MSB first. The
MSB is valid on the first SCLK rising edge after LRCLK
transitions low to high or high to low (Figure 5). Drive
LRCLK high to direct data to OUTL. Drive LRCLK low to
direct data to OUTR. The number of SCLK pulses with
LRCLK high or low determines the number of bits trans-
ferred per sample. If fewer than 24 bits of data are writ-
ten, the remaining LSBs are set to 0. If more than 24
bits are written, the bits after the LSB are ignored.
The MAX5557 accepts up to 24 bits of data in external
serial clock mode and internal serial clock mode.
Program the MCLK/LRCLK ratio to 384 to operate the
internal serial clock at 48 x f
MCLK/LRCLK ratio to 256 or 512 to operate the internal
serial clock at 64 x f
The MAX5558 operates from a 16-bit right-justified data
format. The LSB is valid on the final SCLK rising edge
prior to LRCLK transitioning low to high or high to low
(Figure 6). In external serial clock mode, the MAX5558
requires a minimum of 32 SCLK cycles per LRCLK peri-
od (16 SCLK cycles with LRCLK low and 16 SCLK
cycles with LRCLK high). Drive LRCLK high to direct
data to OUTL. Drive LRCLK low to direct data to OUTR.
Any additional SDATA bits prior to the MSB are ignored.
MAX5558 16-Bit Right-Justified Data Format
MAX5556 I
MAX5557 Left-Justified Data Format
S
.
2
S Left-Justified Data Format
S
) in internal serial
S
Data Formats
. Program the
2
S left-justified
S
).