MAX539BCPA+ Maxim Integrated Products, MAX539BCPA+ Datasheet - Page 12

• Manufacturer Part Number: MAX539BCPA+
• Description: IC DAC V-OUT 12BIT 5V LP 8-DIP
• Manufacturer: Maxim Integrated Products

Specifications of MAX539BCPA+

• Settling Time: 25µs
• Number Of Bits: 12
• Data Interface: Serial
• Number Of Converters: 1
• Voltage Supply Source: Single Supply
• Power Dissipation (max): 727mW
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 8-DIP (0.300", 7.62mm)
• Number Of Dac Outputs: 1
• Resolution: 12 bit
• Interface Type: Serial (SPI)
• Supply Voltage (max): 5.25 V
• Supply Voltage (min): 4.5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: Through Hole
• Maximum Power Dissipation: 471 mW
• Minimum Operating Temperature: 0 C
• Supply Current: 140 uA
• Voltage Reference: External
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

+5V, Low-Power, Voltage-Output,
Serial 12-Bit DACs
Figure 8. Bipolar Configuration (-2.048V to +2.048V Output)
As with any amplifier, the MAX531/MAX538/MAX539’s
output buffer can be positive or negative. When the off-
set is positive, it is easily accounted for (Figure 10).
However, when the offset is negative, the buffer output
cannot follow linearly when there is no negative supply.
In that case, the amplifier output (VOUT) remains at
ground until the DAC voltage is sufficient to overcome
the offset and the output becomes positive.
Normally, linearity is measured after accounting for
zero error and gain error. Since, in single-supply opera-
tion, the actual value of a negative offset is unknown, it
cannot be accounted for during test. Additionally, the
output buffer amplifier exhibits a nonlinearity near-zero
output when operating with a single supply. To account
for this nonlinearity in the MAX531/MAX538/MAX539,
linearity and gain error are measured from code 11 to
code 4095. The output buffer’s offset and nonlinear
behavior do not affect monotonicity, and these DACs
are guaranteed monotonic starting with code zero. In
dual-supply operation, linearity and gain error are mea-
sured from code 0 to 4095.
Best system performance is obtained with printed cir-
cuit boards that use separate analog and digital
ground planes. Wire-wrap boards are not recommend-
ed. The two ground planes should be connected
together at the low-impedance power-supply source.
12
______________________________________________________________________________________
33µF
Power-Supply Bypassing and
REFIN
REFOUT
AGND
DGND
MAX531
Single-Supply Linearity
-5V
+5V
Ground Management
BIPOFF
VOUT
RFB
V
OUT
DGND and AGND should be connected together at the
chip. For the MAX531 in single-supply applications,
connect V
connection may be achieved by connecting the DAC’s
DGND and AGND pins together and connecting that
point to the system analog ground plane. If the DAC’s
DGND is connected to the system digital ground, digi-
tal noise may get through to the DAC’s analog portion.
Bypass V
0.1µF ceramic capacitor, connected between V
AGND (and between V
leads close to the device. Ferrite beads may also be
used to further isolate the analog and digital power
supplies.
Figures 11a and 11b illustrate the grounding and
bypassing scheme described.
When the DAC is not being used by the system, mini-
mize power consumption by setting the appropriate
code to minimize load current. For example, in bipolar
mode, with a resistive load to ground, set the DAC
code to mid-scale (Table 3). If there is no output load,
minimize internal loading on the reference by setting
the DAC to all 0s (on the MAX531, use CLR). Under this
condition, REFIN is high impedance and the op amp
operates at its minimum quiescent current. Due to
these low current levels, the output settling time for an
input code close to 0 typically increases to 60µs (no
more than 100µs).
Table 3. Bipolar (Offset Binary) Code
Table (-V
1111
1000
1000
0111
0000
0000
DD
SS
REFIN
INPUT
1111
0000
0000
1111
0000
0000
to AGND at the chip. The best ground
(and V
1111
0001
0000
1111
0000
0001
to +V
SS
SS
in dual-supply mode) with a
and AGND). Mount with short
REFIN
(+V
(+V
(-V
(-V
(-V
Output)
REFIN
REFIN
REFIN
REFIN
OUTPUT
REFIN
Saving Power
0V
)
)
)
)
)
2048
2048
2047
2048
2048
2048
2047
2048
1
1
= -V
REFIN
DD
and