MAX539BCPA+ Maxim Integrated Products, MAX539BCPA+ Datasheet - Page 9

• Manufacturer Part Number: MAX539BCPA+
• Description: IC DAC V-OUT 12BIT 5V LP 8-DIP
• Manufacturer: Maxim Integrated Products

Specifications of MAX539BCPA+

• Settling Time: 25µs
• Number Of Bits: 12
• Data Interface: Serial
• Number Of Converters: 1
• Voltage Supply Source: Single Supply
• Power Dissipation (max): 727mW
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 8-DIP (0.300", 7.62mm)
• Number Of Dac Outputs: 1
• Resolution: 12 bit
• Interface Type: Serial (SPI)
• Supply Voltage (max): 5.25 V
• Supply Voltage (min): 4.5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: Through Hole
• Maximum Power Dissipation: 471 mW
• Minimum Operating Temperature: 0 C
• Supply Current: 140 uA
• Voltage Reference: External
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The on-chip reference is lesser trimmed to generate 2.048V
at REFOUT. The output stage can source and sink current,
so REFOUT can settle to the correct voltage quickly in
response to code-dependent loading changes. Typically,
source current is 5mA and sink current is 100µA.
REFOUT connects the internal reference to the R-2R DAC
ladder at REFIN. The R-2R ladder draws 50µA maximum
load current. If any other connection is made to REFOUT,
ensure that the total load current is less than 100µA to
avoid gain errors.
For applications requiring very low-noise performance,
connect a 33µF capacitor from REFOUT to AGND. If noise
is not a concern, a lower value capacitor (3.3µF min) may
be used. To reduce noise further, insert a buffered RC filter
between REFOUT and REFIN (Figure 2). The reference
bypass capacitor, C
stability. In applications not requiring the reference, con-
nect REFOUT to V
internal reference).
An external reference in the range (V
may be used with the MAX531 in dual-supply operation.
With the MAX538/MAX539 or the MAX531 in single-supply
use, the reference must be positive and may not exceed
V
scale output. The DAC input resistance is code dependent
and is minimum (40kΩ) at code 555 hex and virtually infi-
Figure 2. Reference Noise vs. Frequency
DD
- 2V. The reference voltage determines the DAC’s full-
300
250
200
150
100
50
0
0.1
C
REFOUT
SINGLE-POLE ROLLOFF
REFOUT
Internal Reference (MAX531 only)
DD
_______________________________________________________________________________________
1
REFOUT
TEK 7A22
FREQUENCY (kHz)
R
C
or use the MAX538 or MAX539 (no
S
S
C
REFOUT
10
, is still required for reference
= 3.3 F
C
REFOUT
External Reference
TOTAL
REFERENCE
NOISE
100
SS
= 47 F
+5V, Low-Power, Voltage-Output,
+ 2V) to (V
1000
0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
DD
- 2V)
nite at code 000 hex. REFIN’s input capacitance is also
code dependent and has a 50pF maximum value at sever-
al codes. Because of the code-dependent nature of refer-
ence input impedances, a high-quality, low-output-imped-
ance amplifier (such as the MAX480 low-power, precision
op amp) should be used.
If an upgrade to the internal reference is required, the 2.5V
MAX873A is suitable: ±15mV initial accuracy, TCV
7ppm/°C (max).
The MAX531/MAX538/MAX539 logic inputs are designed to
be compatible with TTL or CMOS logic levels. However, to
achieve the lowest power dissipation, drive the digital inputs
with rail-to-rail CMOS logic. With TTL logic levels, the power
requirement increases by a factor of approximately 2.
Figure 1 shows the MAX531/MAX538/MAX539 timing. The
maximum serial clock rate is given by 1 / (t
approximately 14MHz. The digital update rate is limited by
the chip-select period, which is 16 x (t
This equals a 1.14µs, or 877kHz, update rate. However, the
DAC settling time to 12 bits is 25µs, which may limit the
update rate to 40kHz for full-scale step transitions.
Refer to Figures 3a and 3b for typical operating connec-
tions.
The MAX531/MAX538/MAX539 use a three-wire serial
interface that is compatible with SPI™, QSPI™
(CPOL = CPHA = 0), and Microwire™ standards as shown
in Figures 4 and 5. The DAC is programmed by writing two
8-bit words (see Figure 1 and the Functional Diagram ).
Sixteen bits of serial data are clocked into the DAC MSB
first with the MSB preceded by four fill (dummy) bits. The
four dummy bits are not normally needed. They are
required only when DACs are daisy-chained. Data is
clocked in on SCLK’s rising edge while CS is low. The seri-
al input data is held in a 16-bit serial shift register. On CS’s
rising edge, the 12 least significant bits are transferred to
the DAC register and update the DAC. With CS high, data
cannot be clocked into the MAX531/MAX538/MAX539.
The MAX531/MAX538/MAX539 input data in 16-bit blocks.
The SPI and Microwire interfaces output data in 8-bit
blocks, thereby requiring two write cycles to input data to
the DAC. The QSPI interface allows variable data input
from eight to 16 bits, and can be loaded into the DAC in
one write cycle.
SPI and QSPI are trademarks of Motorola, Inc.
Microwire is a trademark of National Semiconductor Corp.
____________Applications Information
Serial 12-Bit DACs
Serial Clock and Update Rate
Serial Interface
Logic Interface
CH
+ t
CL
CH
) + t
+ t
OUT
CSW
CL
=
9
),
.