AD9788BSVZ Analog Devices Inc, AD9788BSVZ Datasheet
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AD9788BSVZ
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AD9788BSVZ Summary of contents
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FEATURES Analog output: adjustable 8 31.7 mA Ω Ω L Low power, fine complex NCO allows carrier placement anywhere in DAC bandwidth while adding <300 mW power Auxiliary DACs allow I and Q ...
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AD9785/AD9787/AD9788 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Product Highlights ........................................................................... 1 Typical Signal Chain ......................................................................... 1 Revision History ............................................................................... 2 Specifications ..................................................................................... 3 DC Specifications ......................................................................... 3 Digital Specifications ................................................................... 4 AC Specifications ...
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SPECIFICATIONS DC SPECIFICATIONS AVDD33 = 3.3 V, DVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1 MIN MAX otherwise noted. LVDS driver and receiver are compliant to the IEEE 1596 reduced range ...
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AD9785/AD9787/AD9788 DIGITAL SPECIFICATIONS AVDD33 = 3.3 V, DVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1 MIN MAX otherwise noted. Table 2. Parameter CMOS INPUT LOGIC LEVEL Input V Logic High IN ...
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Parameter LATENCY (DACCLK CYCLES) 1× Interpolation 2× Interpolation 4× Interpolation 8× Interpolation Inverse Sinc 2 POWER-UP TIME 3 DAC Wake-Up Time DAC Sleep Time 4 1 Timing vs. temperature and data valid windows are delineated in Table 25. 2 Measured ...
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AD9785/AD9787/AD9788 ABSOLUTE MAXIMUM RATINGS Table 4. Parameter Rating AVDD33 to AGND, DGND, CGND −0 +3.6 V DVDD33, DVDD18, CVDD18 −0 +2 AGND, DGND, CGND AGND to DGND, CGND −0 +0.3 V DGND ...
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PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS 100 CVDD18 1 PIN 1 INDICATOR CVDD18 2 CGND 3 CGND ...
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AD9785/AD9787/AD9788 Pin No. Mnemonic 29 P1D[1] 30 P1D[ DATACLK 38, 61 DVDD33 39 TXENABLE 40 P2D[11] 41 P2D[10] 42 P2D[9] 45 P2D[8] 46 P2D[7] 47 P2D[6] 48 P2D[5] 49 P2D[4] 50 ...
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CVDD18 1 PIN 1 INDICATOR CVDD18 2 CGND 3 CGND 4 REFCLK+ 5 REFCLK– 6 ...
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AD9785/AD9787/AD9788 Pin No. Mnemonic 31 P1D[1] 34 P1D[0] 35, 36, 58 DATACLK 38, 61 DVDD33 39 TXENABLE 40 P2D[13] 41 P2D[12] 42 P2D[11] 45 P2D[10] 46 P2D[9] 47 P2D[8] 48 P2D[7] 49 P2D[6] 50 P2D[5] 51 P2D[4] ...
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CVDD18 1 PIN 1 INDICATOR CVDD18 2 CGND 3 CGND 4 REFCLK+ 5 REFCLK– 6 ...
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AD9785/AD9787/AD9788 Pin No. Mnemonic 31 P1D[3] 34 P1D[2] 35 P1D[1] 36 P1D[0] 37 DATACLK 38, 61 DVDD33 39 TXENABLE 40 P2D[15] 41 P2D[14] 42 P2D[13] 45 P2D[12] 46 P2D[11] 47 P2D[10] 48 P2D[9] 49 P2D[8] 50 P2D[7] 51 P2D[6] 52 ...
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TYPICAL PERFORMANCE CHARACTERISTICS –142 –146 4× –150 –154 1× –158 –162 –166 –170 (MHz) OUT Figure 5. AD9785 Noise Spectral Density vs 200 MSPS DATA –142 –146 2× –150 –154 –158 1× ...
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AD9785/AD9787/AD9788 –55 –60 –65 –70 FIRST ADJ CHAN –75 SECOND ADJ CHAN –80 –85 THIRD ADJ CHAN – 100 120 140 160 180 200 220 240 260 f (MHz) OUT Figure 11. AD9787 ACLR, 4× ...
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PLL ON –70 –6 dBFS PLL OFF –75 –80 –85 –3 dBFS PLL OFF 0 dBFS PLL OFF – 100 120 140 160 180 200 220 240 f (MHz) OUT ...
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AD9785/AD9787/AD9788 100 90 80 75MSPS 70 50MSPS 100 150 200 250 f (MHz) OUT Figure 23. AD9788 IMD vs 8× Interpolation OUT 100 90 80 0dBFS 120 160 ...
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OUT Figure 29. AD9788 Noise Spectral Density vs 100 MSPS DATA –142 –146 –150 –154 –158 1× –162 –166 –170 ...
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AD9785/AD9787/AD9788 110 100MSPS 100 150MSPS (MHz) OUT Figure 35. AD9788 In-Band SFDR vs 100MSPS 75 150MSPS ...
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OUT Figure 41. AD9788 In-Band SFDR vs 4× Interpolation, f OUT PLL On/PLL Off PLL OFF PLL 100 MSPS, DATA Rev. ...
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AD9785/AD9787/AD9788 TERMINOLOGY Integral Nonlinearity (INL) INL is defined as the maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from zero scale to full scale. Differential Nonlinearity (DNL) DNL is the measure ...
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THEORY OF OPERATION The AD9785/AD9787/AD9788 devices combine many features that make them very attractive DACs for wired and wireless communications systems. The dual digital signal path and dual DAC structure allow an easy interface to common quadrature modulators when designing ...
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AD9785/AD9787/AD9788 There are two phases to a communication cycle with the AD9785/AD9787/AD9788. Phase 1 is the instruction cycle, which is the writing of an instruction byte into the AD9785/ AD9787/AD9788, coincident with the first eight SCLK rising edges. The instruction ...
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Instruction Byte The instruction byte contains the following information as shown in the instruction byte bit map. Instruction Byte Information Bit Map MSB R —Bit 7 of the instruction ...
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AD9785/AD9787/AD9788 SPI REGISTER MAP When reading Table 9, note that the AD9785/AD9787/AD9788 is a 32-bit part and, therefore, the 4 with the MSB and ending with the LSB) represent a set of eight bits. Refer to the Bit Range column ...
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Register Bit Address Name Range MSB 0x0B Phase [15:0] Control [23:16] Register [31:24] 0x0C Amplitude [7:0] Scale [15:8] Factor Register [23:16] 0x0D Output [15:0] Offset [31:16] Register 1 0x0E Version [7:0] Register [15:8] 1 0x1D RAM [31:0] 0x1E Test [23:0] ...
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AD9785/AD9787/AD9788 The digital control (DCTL) register comprises two bytes located at Address 0x01. Table 11. Digital Control (DCTL) Register Address Bit Name 0x01 [15] Reserved [14] Clear phase accumulator [13] PN code sync enable [12] Sync mode select [11] Pulse ...
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The data synchronization control register (DSCR) comprises two bytes located at Address 0x02. Table 12. Data Synchronization Control Register (DSCR) Address Bit Name 0x02 [15:11] DATACLK Delay [4:0] [10:7] Data Timing Margin [3:0] [6] LVDS data clock enable [5] DATACLK ...
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AD9785/AD9787/AD9788 The multichip synchronization register (MSCR) comprises four bytes located at Address 0x03. Table 13. Multichip Synchronization Register (MSCR) Address Bit Name 0x03 [31:27] Correlate Threshold [4:0] [26] SYNC_I enable [25] SYNC_O enable [24] Set low [23:19] SYNC_I Delay [4:0] ...
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The PLL control (PLLCTL) register comprises three bytes located at Address 0x04. These bits are routed directly to the periphery of the digital logic. No digital functionality within the main digital block is required. Table 14. PLL Control (PLLCTL) Register ...
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AD9785/AD9787/AD9788 The Auxiliary DAC 1 control register comprises two bytes located at Address 0x06. These bits are routed directly to the periphery of the digital logic. No digital functionality within the main digital block is required. Table 16. Auxiliary DAC ...
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The interrupt control register comprises two bytes located at Address 0x09. Bits [11:10] and Bits [7:3] are read-only bits that indicate the current status of a specific event that may cause an interrupt request (IRQ pin active low). These bits ...
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AD9785/AD9787/AD9788 The frequency tuning word (FTW) register comprises four bytes located at Address 0x0A. Table 20. Frequency Tuning Word (FTW) Register Address Bit Name 0x0A [31:0] Frequency Tuning Word [31:0] The phase control register (PCR) comprises four bytes located at ...
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INPUT DATA PORTS The AD9785/AD9787/AD9788 can operate in two data input modes: dual-port mode and single-port mode. In the default dual-port mode (single-port mode = 0), each DAC receives data from a dedicated input port. In single-port mode (single-port mode ...
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AD9785/AD9787/AD9788 DATACLK INPUT DATA QFIRST = 0 QFIRST = 1 Table 25. Data Timing Specifications vs. Temperature Timing Parameter Temperature Data with respect to REFCLK −40°C +25°C +85°C −40°C to +85°C Data with respect to DATACLK −40°C +25°C +85°C −40°C ...
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Setting the Frequency of DATACLK The DATACLK signal is derived from the internal DAC sample clock, DACCLK. The frequency of DATACLK output depends on several programmable settings. The relationship between the frequency of DACCLK and DATACLK is f DACCLK ...
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AD9785/AD9787/AD9788 SYNC_I DACCLK REFCLK INPUT DATA OPTIMIZING THE DATA INPUT TIMING The AD9785/AD9787/AD9788 have on-chip circuitry that enables the user to optimize the input data timing by adjusting the relationship between the DATACLK output and DCLK_SMP, the internal clock that ...
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Manual Timing Optimization Mode When the device is operating in manual timing optimization mode (Register 0x02, Bit 3 = 0), the device does not alter the DATACLK Delay [4:0] value that is programmed by the user. By default, the DATACLK ...
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AD9785/AD9787/AD9788 DIGITAL DATAPATH The AD9785/AD9787/AD9788 digital datapath consists of three 2× half-band interpolation filters, a quadrature modulator, and an inverse sinc filter. A 32-bit NCO provides the sine and cosine carrier signals required for the quadrature modulator. INTERPOLATION FILTERS The ...
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Table 28. Half-Band Filter 1 Lower Coefficient Upper Coefficient H(1) H(55) H(2) H(54) H(3) H(53) H(4) H(52) H(5) H(51) H(6) H(50) H(7) H(49) H(8) H(48) H(9) H(47) H(10) H(46) H(11) H(45) H(12) H(44) H(13) H(43) H(14) H(42) H(15) H(41) H(16) ...
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AD9785/AD9787/AD9788 QUADRATURE MODULATOR The quadrature modulator is used to mix the carrier signal generated by the NCO with the upsampled I and Q data provided by the user at the 16-bit parallel input port of the device. Figure 58 shows ...
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Table 31. Inverse Sinc Filter Lower Coefficient Upper Coefficient H(1) H(9) H(2) H(8) H(3) H(7) H(4) H(6) H(5) – The inverse sinc filter is disabled by default. It can be enabled by setting the inverse sinc enable bit (Bit 9) ...
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AD9785/AD9787/AD9788 DEVICE SYNCHRONIZATION System demands may impose two different requirements for synchronization. Some systems require multiple DACs to be synchronized to each other, for example, a system that supports transmit diversity or beamforming, where multiple antennas are used to transmit ...
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NCO PHASE ACCUMULATOR RESET NCO RESET GENERATOR TXENABLE TRANSMIT (PIN 39) PATH SYNC_I t Δ (PIN 13, PIN 14) SYNC_I DELAY [4:0] SYNC_I ENABLE Figure 60. Synchronization Receive Circuitry Block Diagram SYSTEM CLOCK LOW SKEW CLOCK DRIVER PULSE GENERATOR LOW ...
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AD9785/AD9787/AD9788 SYNCHRONIZING DEVICES TO A SYSTEM CLOCK The AD9785/AD9787/AD9788 offer a pulse mode synchron- ization scheme (see Figure 61) to align the DAC outputs of multiple devices within a system to the same DAC clock edge. The pulse mode synchronization ...
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Table 32 shows the register settings required to enable the pulse mode synchronization feature. Table 32. Register Settings for Enabling Pulse Sync Mode Register Bit Parameter 0x01 [13] PN code sync enable [12] Sync mode select [11] Pulse sync enable ...
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AD9785/AD9787/AD9788 Table 33 lists the register settings required to enable the PN code mode synchronization feature. Table 33. Register Settings for Enabling PN Code Mode Register Bit Parameter 0x01 [13] PN code sync enable [12] Sync mode select [11] Pulse ...
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DRIVING THE REFCLK INPUT The REFCLK input requires a low jitter differential drive signal. REFCLK is a PMOS input differential pair powered from the 1.8 V supply; therefore important to maintain the specified 400 mV input common-mode voltage. ...
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AD9785/AD9787/AD9788 (PIN 5 AND PIN 6) Table 35. Typical VCO Freq Range vs. PLL Band Select Value PLL Lock Ranges over Temperature, −40°C to +85°C VCO Frequency Range in MHz PLL Band Select f LOW 111111 (63) Auto mode 111110 ...
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Configuring the PLL Band Select Value The PLL VCO has a valid operating range from approximately 1.0 GHz to 2.0 GHz covered in 63 overlapping frequency bands as shown in Table 35. For any desired VCO output frequency, there are ...
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AD9785/AD9787/AD9788 ANALOG OUTPUTS Full-scale current on the I DAC and Q DAC can be set from 8. 31.66 mA. Initially, the 1.2 V band gap reference is used to set up a current in an external resistor connected ...
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There are two output signals on each auxiliary DAC. One signal is designated P, the other N. The sign bit in each auxiliary DAC control register (Bit 15) controls whether the P side or the N side of the auxiliary ...
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AD9785/AD9787/AD9788 POWER DISSIPATION Figure 74 through Figure 78 detail the power dissipation of the AD9785/AD9787/AD9788 under a variety of operating conditions. All of the graphs are taken with data being supplied to both the I and Q channels. The power ...
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DAC Figure 78. Digital 1.8 V Supply, Power Dissipation of Inverse Sinc Filter 800 1000 Rev Page AD9785/AD9787/AD9788 ...
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AD9785/AD9787/AD9788 AD9785/AD9787/AD9788 EVALUATION BOARDS The remainder of this data sheet describes the evaluation boards for testing the AD9785, AD9787, and AD9788 devices. OUTPUT CONFIGURATION Each evaluation board contains an Analog Devices ADL5372 quadrature modulator. The AD9785/AD9787/AD9788 devices and the ADL5372 ...
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EVALUATION BOARD SOFTWARE A GUI .exe file for Microsoft® Windows® is included on the CD that ships with the evaluation board. This file allows the user to easily program all the functions on the AD9785/AD9787/AD9788. INTERPOLATION AND FILTER MODE SETTINGS ...
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AD9785/AD9787/AD9788 EVALUATION BOARD SCHEMATICS Figure 81. Evaluation Board, Power Supply and Decoupling Rev Page 07098-044 RC080 5 5 RC080 ...
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ACA E S ACA CC 040 2 CC 040 2 P1D15 P1D14 P1D13 P1D12 P1D11 P1D10 P1D9 P1D8 RC 060 3 P1D7 P1D6 RC 060 ...
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AD9785/AD9787/AD9788 DNP RC0603 R24 PAD DNP RC0603 RC0603 R23 Figure 83. Evaluation Board, ADL5372 (FMOD2) Quadrature Modulator Rev Page 07098-046 100PF C73 C54 10 3 ...
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RC040 2 RC040 2 RC040 2 RC040 2 2 CC040 2 CC040 2 RC040 Figure 84. Evaluation Board, TxDAC Clock Interface Rev Page AD9785/AD9787/AD9788 ...
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AD9785/AD9787/AD9788 Figure 85. Evaluation Board, Digital Input Data Lines Rev Page 07098-048 ...
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Figure 86. Evaluation Board, On-Board Power Supply Rev Page AD9785/AD9787/AD9788 07098-049 ...
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... AD9785BSVZ −40C to +85C AD9785BSVZRL 1 −40C to +85C 1 AD9787BSVZ −40C to +85C 1 AD9787BSVZRL −40C to +85C AD9788BSVZ 1 −40C to +85C 1 AD9788BSVZRL −40C to +85C 1 AD9785-EBZ 1 AD9787-EBZ 1 AD9788-EBZ 1 RoHS Compliant Part. 16.00 BSC SQ 14.00 BSC SQ 100 76 1 ...
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NOTES AD9785/AD9787/AD9788 Rev Page ...
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AD9785/AD9787/AD9788 NOTES ©2008–2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07098-0-2/09(A) Rev Page ...