AD5452YRM Analog Devices Inc, AD5452YRM Datasheet - Page 21

• Manufacturer Part Number: AD5452YRM
• Description: IC DAC 12BIT MULTIPLYING 8-MSOP
• Manufacturer: Analog Devices Inc

Specifications of AD5452YRM

• Design Resources: Unipolar, Precision DC Digital-to-Analog Conversion using AD5450/1/2/3 8-14-Bit DACs (CN0052) Precision, Bipolar, Configuration for AD5450/1/2/3 8-14bit Multiplying DACs (CN0053) AC Signal Processing Using AD5450/1/2/3 Current Output DACs (CN0054) Programmable Gain Element Using AD5450/1/2/3 Current Output DAC Family (CN0055) Single Supply Low Noise LED Current Source Driver Using a Current Output DAC in the Reverse Mode (CN0139)
• Settling Time: 160ns
• Number Of Bits: 12
• Data Interface: Serial
• Number Of Converters: 1
• Voltage Supply Source: Single Supply
• Power Dissipation (max): 55µW
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 8-MSOP, Micro8™, 8-uMAX, 8-uSOP,
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

SERIAL INTERFACE
The AD5 0/AD5451/AD5452/A 5453 have an easy-to- e
3-wire in face
and most DSP in
16-bit w
10, 12, or
and Figu 53. The AD5453 us
AD5452
uses 10
8 bits an gno
DAC Con rol
Control B
new DAC od
th
changed via the control bits. If changed, the D
inoperative until the next data frame, and a po
required t
resets the c
circuitry e
loaded to
Table 10
C1
0
0
1
1
SYNC Function
SYNC is an e
synchron
tr
data transfer, SYNC should be taken low, observing the
m
m
powers up fully only when the device is being written to, that is,
u
b
A
to transfer data from the input shift register to the DAC register.
pon the falling edge of SYNC
uffers are powered down upon the rising edge of SYNC
ansferred to the device while SYNC
fter the falling edge of the 16
e shift register clocks data upon the falling edge; this can be
inimum SYNC
inimize the power consumption of the device, the interface
C0
0
1
0
1
bits and ignores the four LS
ord
d i
ter
re
14
us
. D
45
izat
o r
t
its C1 and C0 allow the u
th
ns
c e and to change the a
o
es 12
s. T
dat
e DAC register an
AC Cont
re to default condition
ures that the
eturn it to active on t
ion signal
dge-trigg
Functio
Load and update (power-on default)
Reserved
Reserved
Clock data to shift regis ter upon rising edge
Bits C1, C0
a bits, as shown in Fig
res the six LSBs.
his 16-bit word cons
that is compatible w
terface standards. D
bits and ignores th
falling to SCLK falling edge setup time, t
n Implemented
rol Bits
ered input tha
and chip enab
device pow
d I
th
. The SCLK and SDIN input
es al
SCLK pulse, bring SYNC
OUT
he fallin
D
. O
ure 50
l 14 bi
ser to
ctive c
ists o
e two
Bs, and t
ith SP
ata is wr
l
t acts a
ers o
ine.
le. Da
n-chip power-o
is low. To start the serial
f two control bits an
I, QSPI, MICROW
ts of DAC data, the
load and update th
, Figure 51, Figure
LSBs, the AD5451
lock edge. By defa
n with zero sc
g edge. A p
ta can only be
s a frame-
itten to the devic
he AD5450 use
AC core is
wer recycle is
ower c
n r
ale
eset
.
us
high
4
. To
s
ult,
ycle
e in
52,
IRE,
e
Rev. E | Page 21 of 32
d 8
,
The serial interface to the AD5450 uses a 16-bit shift register.
Take care
latched to up te the DA
For example
•
•
•
Also n
SYN goes high the las
CONTROL BITS
CONTROL BITS
CONTROL BITS
DB15 (MSB)
CONTROL BITS
DB15 (MSB)
DB15 (MSB)
DB15 (MSB)
CONTROL BITS
C1
C1
C1
C1
0
C
Loadin
the out
User in
SYNC
actually
The user expects an
goes hig
data seq
register t
and used as the 4 MSBs missing. The addition of these
4 bits will put the part in rising edge mode and the output
will show n
show the da
C0
C0
Figure 54. AD5453 First Write, Complete Data Sequence (0x3FFF)
C0
C0 DB13 DB12
0
ote that if more t
DB11 DB10
DB7 DB6 DB5 DB4
DB9
to
Figur
Figure 52. AD5452 12-Bit Input Shift Register Contents
Figure 53. AD5453 14-Bit Input Shift Register Contents
1
Figure 50. AD5450 8-Bit Input Shift Register Contents
AD5450/AD5451/AD5452/AD5453
g
g 0
put
,
ten
avoid inco plete data sequences as ese will be
DB8
da
oes hig
uence o
h afte
upda
he 4 LSBs f
1
e 51. AD5451
x3FFF (a
ds to wri 0x3200 but after 12 act
to 10 V
DB11
o change. Figure 54, Figure 55, and Table 11
DB9
DB7 DB6
ta fram
1
te the
r 12 va id clock edges then an i
h (in
DB10
DB8
f 12 bits is loaded. To complet
1
m
hen 1
t 16-b
(fu
te
es for this example.
DB3
D
DB7 DB6 DB5 DB4 DB3 DB2
DB9 DB8 DB7 DB6 DB5 DB4
foll
C o
com
com
ro
B5 DB4 DB3
ou
l
10-Bit In
1
ll scale).
m the previous sequence
owing code: 0xF200.
tput of 5.6 V. Howeve
DB2
utput.
6-bits are loaded to th
plete data sequence)
its will be latched.
DATA BITS
DATA BITS
DATA BITS
DATA BITS
plete write sequence
1
DATA BITS
DB1
put Shift Re
1
DB0
DB2 DB1
1
X
1
gister Contents
DB0
X
1
DB1
DB3
th
X
X
1
ive edges
). This will
r, if SYN
ncomplete
e part b
will update
e the sh
DB0
DB2
X
X
are tak
1
DB1
DB0 (LSB)
DB0 (LSB)
DB0 (LSB)
DB0 (LSB)
X
X
X
1
efore
C
if
DB0
en
X
t
X
X
1