AD8802AR Analog Devices Inc, AD8802AR Datasheet - Page 7

• Manufacturer Part Number: AD8802AR
• Description: IC DAC 8BIT 12CH W/SD 20-SOIC
• Manufacturer: Analog Devices Inc
• Series: TrimDAC®r

Specifications of AD8802AR

• Settling Time: 600ns
• Rohs Status: RoHS non-compliant
• Number Of Bits: 8
• Data Interface: Serial
• Number Of Converters: 12
• Voltage Supply Source: Single Supply
• Power Dissipation (max): 60µW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-SOIC (7.5mm Width)
• Number Of Channels: 12
• Resolution: 8b
• Interface Type: Serial (3-Wire/SPI)
• Single Supply Voltage (typ): 3/5V
• Dual Supply Voltage (typ): Not RequiredV
• Architecture: R-2R
• Power Supply Requirement: Single
• Output Type: Voltage
• Single Supply Voltage (min): 2.7V
• Single Supply Voltage (max): 5.5V
• Dual Supply Voltage (min): Not RequiredV
• Dual Supply Voltage (max): Not RequiredV
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 20
• Lead Free Status / RoHS Status: Not Compliant

REV. 0
PROGRAMMING THE OUTPUT VOLTAGE
The output voltage range is determined by the external refer-
ence connected to V
simplified diagram of the equivalent DAC circuit. In the case of
the AD8802 its V
therefore cannot be offset. V
can be tied to GND establishing a basic rail-to-rail voltage out-
put programming range. Other output ranges are established by
the use of different external voltage references. The general
transfer equation which determines the programmed output
voltage is:
where Dx is the data contained in the 8-bit DACx register.
For example, when V
ing output voltages will be generated for the following codes:
D
255
128
1
0
REFERENCE INPUTS (V
The reference input pins set the output voltage range of all
twelve DACs. In the case of the AD8802 only the V
available to establish a user designed full-scale output voltage.
The external reference voltage can be any value between 0 and
V
has access to the V
voltage, any voltage can be applied between 0 V and V
can be smaller or larger in voltage than V
design uses fully bidirectional switches as shown in Figure 16.
The input resistance to the DAC has a code dependent variation
which has a nominal worst case measured at 55
proximately 1.2 k . When V
REFL reference must be able to sink current out of the DAC
DD
Figure 16. AD8802/AD8804 Equivalent TrimDAC Circuit
V
V
GND
REFL
REFH
VO (Dx) = (Dx)/256
but must not exceed the V
REGISTER
DAC
TO OTHER DACS
VOx
4.98 V
2.50 V
0.02 V
0.00 V
D7
D6
D0
REFL
REFL
. .
.
REFH
. .
.
P CH
N CH
REFH
is internally connected to GND and
which establishes the zero-scale output
and V
= +5 V and V
REFH
(V
REFH
REFH
Output State
(V
Full Scale
Half Scale (Midscale Reset Value)
1 LSB
Zero Scale
REFH
DD
REFL
, V
REFH
can be tied to V
is greater than V
supply voltage. The AD8804
REFL
MSB
– V
pins. See Figure 16 for a
= +5 V, V
REFL
)
REFL
REFH
) + V
LSB
= 0 V, the follow-
since the DAC
H
REFL
REFL
, which is ap-
DD
2R
2R
2R
REFL
2R
REFH
= 0 V)
and V
. .
.
DD
, the
R
R
pin is
. V
REFL
Eq. 1
REFL
O
X
–7–
ladder, while the REFH reference is sourcing current into the
DAC ladder. The DAC design minimizes reference glitch cur-
rent maintaining minimum interference between DAC channels
during code changes.
DAC OUTPUTS (O1–O12)
The twelve DAC outputs present a constant output resistance of
approximately 5 k independent of code setting. The distribu-
tion of R
However device-to-device matching is process lot dependent
having a 20% variation. The change in R
has a 500 ppm/ C temperature coefficient. During power shut-
down all twelve outputs are open-circuited.
DIGITAL INTERFACING
The AD8802/AD8804 contains a standard three-wire serial in-
put control interface. The three inputs are clock (CLK), CS and
serial data input (SDI). The positive-edge sensitive CLK input
requires clean transitions to avoid clocking incorrect data into
the serial input register. Standard logic families work well. If
mechanical switches are used for product evaluation, they
should be debounced by a flip-flop or other suitable means. Fig-
ure 17 block diagram shows more detail of the internal digital
circuitry. When CS is taken active low, the clock can load data
into the serial register on each positive clock edge, see Table II.
CS
1
0
P
P = Positive Edge, X = Don’t Care.
The data setup and data hold times in the specification table
determine the data valid time requirements. The last 12 bits of
the data word entered into the serial register are held when CS
returns high. At the same time CS goes high it gates the address
decoder which enables one of the twelve positive-edge triggered
DAC registers, see Figure 18 detail.
CLK
X
P
1
SHDN
OUT
CLK
SDI
CS
Table II. Input Logic Control Truth Table
from DAC-to-DAC typically matches within 1%.
Register Activity
No effect.
Shifts Serial Register One bit loading the next bit
in from the SDI pin.
Clock should be high when the CS returns to the
inactive state.
D
GND
REG
SER
D10
D11
Figure 17. Block Diagram
D9
D8
D7
D0
(AD8802 ONLY)
ADDR
DEC
EN
8
RS
AD8802/AD8804
D7
D0
D7
D0
AD8802/AD8804
REG
DAC
REG
DAC
#12
#1
R
R
(AD8804 ONLY)
V
REFL
OUT
DAC
DAC
12
1
with temperature
V
V
O1
O2
O3
O4
O5
O6
O7
O8
O9
O10
O11
O12
DD
REFH