CS43L42-KZZ Cirrus Logic Inc, CS43L42-KZZ Datasheet - Page 16

• Manufacturer Part Number: CS43L42-KZZ
• Description: IC DAC W/HDPN AMP LV 24TSSOP
• Manufacturer: Cirrus Logic Inc

Specifications of CS43L42-KZZ

• Number Of Bits: 24
• Data Interface: Serial
• Number Of Converters: 2
• Voltage Supply Source: Single Supply
• Power Dissipation (max): 41mW
• Operating Temperature: -10°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 24-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Settling Time: -
• Other names: 598-1651

4. REGISTER DESCRIPTION
Note:
4.1 Power and Muting Control (address 01h)
4.1.1 AUTO-MUTE (AMUTE)
4.1.2 SOFT RAMP AND ZERO CROSS CONTROL (SZC)
16
AMUTE
Function:
Function:
7
1
All registers are read/write in Two-Wire mode and write only in SPI, unless otherwise noted.
Immediate Change
Zero Cross Digital and Analog
Ramped Digital and Analog
Note:
Default = 1
0 - Disabled
1 - Enabled
The Digital-to-Analog converter output will mute following the reception of 8192 consecutive audio sam-
ples of static 0 or -1. A single sample of non-static data will release the mute. Detection and muting is
done independently for each channel. The quiescent voltage on the output will be retained and the Mute
Control pin will go active during the mute period. The muting function is affected, similar to volume control
changes, by the Soft and Zero Cross bits in the Power and Muting Control register.
Default = 10
00 - Immediate Change
01 - Zero Cross Digital and Analog
10 - Ramped Digital and Analog
11 - Reserved
When Immediate Change is selected all level changes will take effect immediately in one step.
Zero Cross Enable dictates that signal level changes, either by attenuation changes or muting, will occur
on a signal zero crossing to minimize audible artifacts. The requested level change will occur after a
timeout period of 512 sample periods (10.7 ms at 48 kHz sample rate) if the signal does not encounter a
zero crossing. The zero cross function is independently monitored and implemented for each channel.
Soft Ramp allows digital level changes, both muting and attenuation, to be implemented by incrementally
ramping, in 1/8 dB steps, from the current level to the new level at a rate of 1 dB per 8 left/right clock pe-
riods. Analog level changes will occur in 1 dB steps on a signal zero crossing. The analog level change
will occur after a timeout period of 512 sample periods (10.7 ms at 48 kHz sample rate) if the signal does
not encounter a zero crossing. The zero cross function is independently monitored and implemented for
each channel.
Ramped Digital and Analog is not available in High-Rate Mode.
SZC1
6
1
SZC0
5
0
POR
4
1
PDNHP
3
0
PDNLN
2
0
PDN
1
1
CS43L42
RESERVED
DS481PP2
0
0