AD5663RBRMZ-3 Analog Devices Inc, AD5663RBRMZ-3 Datasheet - Page 9

• Manufacturer Part Number: AD5663RBRMZ-3
• Description: IC DAC NANO 16BIT 1.25V 10-MSOP
• Manufacturer: Analog Devices Inc
• Series: nanoDAC™r

Specifications of AD5663RBRMZ-3

• Data Interface: Serial
• Settling Time: 4µs
• Number Of Bits: 16
• Number Of Converters: 2
• Voltage Supply Source: Single Supply
• Power Dissipation (max): 5mW
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 10-MSOP, Micro10™, 10-uMAX, 10-uSOP
• Resolution (bits): 16bit
• Sampling Rate: 220kSPS
• Input Channel Type: Serial
• Supply Voltage Range - Analog: 2.7V To 3.6V, 4.5V To 5.5V
• Supply Current: 800µA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-AD5663REBZ - BOARD EVAL FOR AD5663
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 7. Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
8
9
10
Mnemonic
V
V
GND
LDAC
CLR
SYNC
SCLK
DIN
V
V
OUT
OUT
DD
REFIN
A
B
/V
REFOUT
Description
Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.
Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.
Ground. Reference point for all circuitry on the part.
Pulsing this pin low allows any or all DAC registers to be updated if the input registers have new data.
This allows simultaneous update of all DAC outputs. Alternatively, this pin can be tied permanently low.
Asynchronous Clear Input. The CLR input is falling edge sensitive. While CLR is low, all LDAC pulses are
ignored. When CLR is activated, zero scale is loaded to all input and DAC registers. This clears the output to 0 V.
The part exits clear code mode on the 24th falling edge of the next write to the part. If CLR is activated during
a write sequence, the write is aborted.
Level-Triggered Control Input (Active Low). This is the frame synchronization signal for the input data.
When SYNC goes low, it enables the input shift register, and data is transferred in on the falling edges of the
following clocks. The DAC is updated following the 24th clock cycle unless SYNC is taken high before this edge,
in which case the rising edge of SYNC acts as an interrupt and the write sequence is ignored by the DAC.
Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input.
Data can be transferred at rates up to 50 MHz.
Serial Data Input. This device has a 24-bit shift register. Data is clocked into the register on the falling edge
of the serial clock input.
Power Supply Input. These parts can be operated from 2.7 V to 5.5 V, and the supply should be decoupled with
a 10 μF capacitor in parallel with a 0.1 μF capacitor to GND.
Common Reference Input/Reference Output. When the internal reference is selected, this is the reference output
pin. When using an external reference, this is the reference input pin. The default for this pin is a reference input.
V
V
LDAC
OUT
OUT
GND
CLR
NOTE:
EXPOSED PAD TIED TO GND ON
LFCSP PACKAGE.
A
B
Figure 3. Pin Configuration
1
2
3
4
5
(Not to Scale)
AD5623R/
AD5643R/
AD5663R
Rev. C | Page 9 of 28
TOP VIEW
10
9
8
7
6
V
V
DIN
SCLK
SYNC
REFIN
DD
/V
REFOUT
AD5623R/AD5643R/AD5663R