AD5422AREZ Analog Devices Inc, AD5422AREZ Datasheet
AD5422AREZ
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AD5422AREZ Summary of contents
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FEATURES 12-/16-bit resolution and monotonicity Current output ranges mA mA ±0.01 % FSR typical total unadjusted error (TUE) ±3 ppm/°C output drift Voltage output ranges ...
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AD5412/AD5422 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Functional Block Diagram .............................................................. 3 Specifications ..................................................................................... 4 AC Performance Characteristics ................................................ 7 Timing Characteristics ................................................................ 8 Absolute Maximum Ratings .......................................................... 10 ...
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FUNCTIONAL BLOCK DIAGRAM DV CC SELECT DV CC CLEAR AD5412/AD5422 SELECT CLEAR LATCH INPUT SHIFT 12/16 SCLK 12-/16-BIT REGISTER DAC AND CONTROL SDIN LOGIC SDO POWER-ON VREF RESET REFOUT REFIN SET RANGE SCALING GND ...
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AD5412/AD5422 SPECIFICATIONS −26 −3 V kΩ 200 pF OUT LOAD L OUT Table 2. 1 ...
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Parameter DC PSRR CURRENT OUTPUT Output Current Ranges Accuracy (Internal R ) SET Resolution Total Unadjusted Error (TUE) B Version A Version 4 Relative Accuracy (INL) Differential Nonlinearity (DNL) Offset Error Offset Error Temperature 3 Coefficient (TC) Gain Error ...
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AD5412/AD5422 1 Parameter 3 OUTPUT CHARACTERISTICS Current Loop Compliance Voltage Output Current Drift vs. Time Resistive Load Inductive Load DC PSRR Output Impedance Output Current Leakage When Output Is Disabled REFERENCE INPUT/OUTPUT 3 Reference Input Reference Input Voltage DC Input ...
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Parameter Power Dissipation 1 Temperature range: −40°C to +85°C; typical at +25°C. 2 When the AD5412/AD5422 is powered with AV for the AD5412. 3 Guaranteed by design and characterization; not production tested. 4 ...
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AD5412/AD5422 TIMING CHARACTERISTICS −26 −3 V kΩ 200 pF OUT LOAD L OUT Table 4. ...
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SCLK LATCH SDIN CLEAR I /V OUT OUT t 11 SCLK LATCH SDIN DB23 INPUT WORD SPECIFIES REGISTER TO BE READ SDO UNDEFINED DATA SCLK 1 2 LATCH SDIN DB23 ...
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AD5412/AD5422 ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. Transient currents not cause SCR latch-up. Table 5. Parameter Rating AV to GND −0 + GND +0.3 ...
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PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS FAULT 3 GND AD5412/ 4 AD5422 CLEAR SELECT 5 TOP VIEW CLEAR 6 (Not to Scale) LATCH 7 SCLK 8 SDIN 9 SDO 10 GND 11 GND 12 NOTES ...
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AD5412/AD5422 Pin No. TSSOP LFCSP Mnemonic SELECT COMP OUT 20 27 BOOST N/A 28, 29 CAP1, CAP2 OUT SENSE 23 34 −V SENSE 24 ...
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TYPICAL PERFORMANCE CHARACTERISTICS GENERAL 900 T = 25°C 800 A 700 600 500 400 300 200 100 0 0 0.5 1.0 1.5 2.0 2.5 3.0 LOGIC VOLTAGE (V) Figure 7. DI vs. ...
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AD5412/AD5422 1 CH1 20µV M2.00s Figure 13. REFOUT Output Noise (100 kHz Bandwidth) 5.003 50 DEVICES SHOWN AV = 24V DD 5.002 5.001 5.000 4.999 4.998 4.997 –40 – TEMPERATURE (°C) Figure 14. Reference Voltage vs. Temperature LINE ...
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VOLTAGE OUTPUT 0.0025 AV = +24V –24V 0.0020 25°C A 0.0015 0.0010 0.0005 0 –0.0005 –0.0010 ±10V RANGE –0.0015 ±5V RANGE +5V RANGE –0.0020 +10V RANGE –0.0025 0 10,000 20,000 30,000 40,000 CODE Figure ...
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AD5412/AD5422 0.0015 AV = +24V –24V SS 0.0010 0.0005 0 –0.0005 –0.0010 +5V RANGE MAX INL ±5V RANGE MAX INL +5V RANGE MIN INL ±5V RANGE MIN INL –0.0015 –40 – TEMPERATURE (°C) Figure 23. ...
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AVDD = +24V AVSS = –24V 0.012 OUTPUT UNLOADED 0.010 0.008 0.006 0.004 0.002 0 –0.002 +5V RANGE –0.004 +10V RANGE ±5V RANGE –0.006 ±10V RANGE –0.008 –40 – TEMPERATURE (°C) Figure 29. Gain Error vs. ...
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AD5412/AD5422 0. +15V 0. –15V 25°C 0.03 A ±10V RANGE 0.02 0.01 0 –0.01 –0.02 –0.03 –0.04 –0.05 –20 –15 –10 –5 0 SOURCE/SINK CURRENT (mA) Figure 35. Source and Sink Capability ...
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CH1 5.0µV M 5.00ms Figure 39. Peak-to-Peak Noise (0 Bandwidth CH1 50.0µV M 5.00ms Figure 40. Peak-to-Peak Noise (100 kHz Bandwidth ...
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AD5412/AD5422 CURRENT OUTPUT EXTERNAL R 0.004 SET INTERNAL R SET EXTERNAL R , BOOST TRANSISTOR SET 0.002 INTERNAL R , BOOST TRANSISTOR SET 0 –0.002 –0.004 –0.006 AV = 24V –24V/0V –0.008 25°C A ...
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AV = 24V –24V/0V SS 0.05 0 –0.05 –0.10 4mA TO 20mA INTERNAL R SET 0mA TO 20mA INTERNAL R –0.15 SET 0mA TO 24mA INTERNAL R SET 4mA TO 20mA EXTERNAL R SET –0.20 0mA ...
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AD5412/AD5422 1.0 0 25°C A 0.6 0mA TO 24mA RANGE 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1 (V) DD Figure 54. Differential Nonlinearity Error vs. AV 0.025 T ...
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T = 25° 40V OUTPUT DISABLED 0 – COMPLIANCE VOLTAGE (V) Figure 60. Output Leakage Current vs. Compliance ...
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AD5412/AD5422 TERMINOLOGY Relative Accuracy or Integral Nonlinearity (INL) For the DAC, relative accuracy, or INL measure of the maximum deviation, in LSBs, from a straight line passing through the endpoints of the DAC transfer function. A typical INL ...
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Power Supply Rejection Ratio (PSRR) PSRR indicates how the output of the DAC is affected by changes in the power supply voltage. Voltage Reference TC Voltage reference measure of the change in the reference output voltage with ...
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AD5412/AD5422 THEORY OF OPERATION The AD5412/AD5422 are precision digital-to-current loop and voltage output converters designed to meet the requirements of industrial process control applications. They provide a high precision, fully integrated, low cost single-chip solution for generating current loop and ...
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SERIAL INTERFACE The AD5412/AD5422 are controlled over a versatile 3-wire serial interface that operates at clock rates MHz compatible with SPI, QSPI™, MICROWIRE, and DSP standards. Input Shift Register The input shift register is ...
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AD5412/AD5422 Readback Operation Readback mode is invoked by setting the address byte and read address when writing to the input register (see Table 9 and Table 11). The next write to the AD5412/AD5422 should be a NOP command, which clocks ...
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DATA REGISTER The data register is addressed by setting the address word of the input shift register to 0x01. The data to be written to the data register is entered in the D15 to D4 positions for the AD5412 and ...
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AD5412/AD5422 RESET REGISTER The reset register is addressed by setting the address word of the input shift register to 0x56. The data to be written to the reset register is entered in the D0 position as shown in Table 17. ...
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AD5412/AD5422 FEATURES FAULT ALERT The AD5412/AD5422 are equipped with a FAULT pin, which is an open-drain output allowing several AD5412/AD5422 devices to be connected together to one pull-up resistor for global fault detection. The FAULT pin is forced active by ...
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AD5412/AD5422 DIGITAL POWER SUPPLY By default, the DV pin accepts a power supply of 2 5.5 V. Alternatively, via the DV SELECT pin, an internal 4 power supply can be output on the DV CC ...
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AD5410/AD5420 registers. The update clock frequency for any given value is the same for all output ranges. The step size, however, varies across output ranges for a given value of step size because the LSB size is different for each ...
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AD5412/AD5422 Table 24. Programmable Slew Time Values in Seconds for a Full-Scale Change on Any Output Range Update Clock Frequency (Hz 257,730 0.25 0.13 198,410 0.33 0.17 152,440 0.43 0.21 131,580 0.50 0.25 115,740 0.57 0.28 69,440 0.9 ...
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APPLICATIONS INFORMATION DRIVING INDUCTIVE LOADS When driving inductive or poorly defined loads, connect a 0.01 μF capacitor between I and GND. This ensures stability OUT with loads above 50 mH. There is no maximum capacitance limit. The capacitive component of ...
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AD5412/AD5422 The power supply lines of the AD5412/AD5422 should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. Fast switching signals such as clocks should be ...
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INDUSTRIAL ANALOG OUTPUT MODULE Many industrial control applications have requirements for accurately controlled current and voltage output signals. The AD5412/AD5422 are ideal for such applications. Figure 77 shows the AD5412/AD5422 in a circuit design for an output module, specifically for ...
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AD5412/AD5422 OUTLINE DIMENSIONS 7.90 7.80 7. TOP VIEW 1.20 MAX 0.15 0.65 SEATING 0.05 BSC PLANE 0.10 COPLANARITY Figure 78. 24-Lead Thin Shrink Small Outline Package, Exposed Pad [TSSOP_EP] PIN 1 INDICATOR 12° MAX 1.00 0.85 0.80 SEATING ...
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... AD5412AREZ-REEL7 12 Bits 0.5% FSR max AD5412ACPZ-REEL 12 Bits 0.5% FSR max AD5412ACPZ-REEL7 12 Bits 0.5% FSR max AD5422AREZ 16 Bits 0.5% FSR max AD5422AREZ-REEL 16 Bits 0.5% FSR max AD5422BREZ 16 Bits 0.3% FSR max AD5422BREZ-REEL 16 Bits 0.3% FSR max AD5422ACPZ-REEL 16 Bits 0.5% FSR max AD5422ACPZ-REEL7 16 Bits 0 ...
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AD5412/AD5422 NOTES ©2009-2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06996-0-3/10(C) Rev Page ...