AD9760AR50 Analog Devices Inc, AD9760AR50 Datasheet - Page 17

• Manufacturer Part Number: AD9760AR50
• Description: IC DAC 10BIT 50MSPS 28-SOIC
• Manufacturer: Analog Devices Inc
• Series: TxDAC®r

Specifications of AD9760AR50

• Rohs Status: RoHS non-compliant
• Settling Time: 35ns
• Number Of Bits: 10
• Number Of Converters: 1
• Voltage Supply Source: Analog and Digital
• Power Dissipation (max): 175mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-SOIC (7.5mm Width)
• Resolution (bits): 10bit
• Input Channel Type: Parallel
• Digital Ic Case Style: SOIC
• No. Of Pins: 28
• Operating Temperature Range: -40°C To +85°C
• Msl: MSL 3 - 168 Hours
• Data Interface: Parallel
• For Use With: AD9760-EBZ - BOARD EVAL FOR AD9760
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

I
ance range is adhered to. One additional consideration in this
mode is the integral nonlinearity (INL) as discussed in the Ana-
log Output section of this data sheet. For optimum INL perfor-
mance, the single-ended, buffered voltage output configuration
is suggested.
SINGLE-ENDED, BUFFERED VOLTAGE OUTPUT
CONFIGURATION
Figure 54 shows a buffered single-ended output configuration
in which the op amp U1 performs an I-V conversion on the
AD9760 output current. U1 maintains I
virtual ground, thus minimizing the nonlinear output impedance
effect on the DAC’s INL performance as discussed in the Ana-
log Output section. Although this single-ended configuration
typically provides the best dc linearity performance, its ac distor-
tion performance at higher DAC update rates may be limited by
U1’s slewing capabilities. U1 provides a negative unipolar out-
put voltage and its full-scale output voltage is simply the product
of R
U1’s voltage output swing capabilities by scaling I
R
with a reduced I
to sink will be subsequently reduced.
POWER AND GROUNDING CONSIDERATIONS
In systems seeking to simultaneously achieve high speed and
high performance, the implementation and construction of the
printed circuit board design is often as important as the circuit
design. Proper RF techniques must be used in device selection,
placement and routing, and supply bypassing and grounding.
The evaluation board for the AD9760, which uses a four-layer
PC board, serves as a good example for the above-mentioned
considerations. Figures 60–65 illustrate the recommended
printed circuit board ground, power and signal plane layouts
that are implemented on the AD9760 evaluation board.
Proper grounding and decoupling should be a primary objective
in any high speed, high resolution system. The AD9760 features
separate analog and digital supply and ground pins to optimize
REV. B
OUTFS
FB
AD9760
. An improvement in ac distortion performance may result
Figure 53. 0 V to +0.5 V Unbuffered Voltage Output
FB
and R
and I
Figure 54. Unipolar Buffered Voltage Output
I
I
OUTA
OUTB 21
AD9760
OUTFS
22
I
I
LOAD
OUTA
OUTB 21
OUTFS
I
22
OUTFS
can be selected as long as the positive compli-
. The full-scale output should be set within
I
OUTFS
since the signal current U1 will be required
= 10mA
= 20mA
25
200
50
200
C
R
U1
OPT
FB
OUTA
V
OUTA
(or I
50
V
= 0 TO +0.5V
OUT
OUTFS
OUTB
= I
OUTFS
) at a
and/or
R
FB
–17–
the management of analog and digital ground currents in a
system. In general, AVDD, the analog supply, should be de-
coupled to ACOM, the analog common, as close to the chip as
physically possible. Similarly, DVDD, the digital supply, should
be decoupled to DCOM as close as physically possible.
For those applications that require a single +5 V or +3 V supply
for both the analog and digital supply, a clean analog supply
may be generated using the circuit shown in Figure 55. The
circuit consists of a differential LC filter with separate power
supply and return lines. Lower noise can be attained using low
ESR type electrolytic and tantalum capacitors.
Maintaining low noise on power supplies and ground is critical
to obtain optimum results from the AD9760. If properly imple-
mented, ground planes can perform a host of functions on high
speed circuit boards: bypassing, shielding, current transport,
etc. In mixed signal design, the analog and digital portions of
the board should be distinct from each other, with the analog
ground plane confined to the areas covering the analog signal
traces, and the digital ground plane confined areas covering the
digital interconnects.
All analog ground pins of the DAC, reference and other analog
components should be tied directly to the analog ground plane.
The two ground planes should be connected by a path 1/8 to
1/4 inch wide underneath or within 1/2 inch of the DAC to
maintain optimum performance. Care should be taken to ensure
that the ground plane is uninterrupted over crucial signal paths.
On the digital side, this includes the digital input lines running
to the DAC as well as any clock signals. On the analog side, this
includes the DAC output signal, reference signal and the supply
feeders.
The use of wide runs or planes in the routing of power lines is
also recommended. This serves the dual role of providing a low
series impedance power supply to the part and providing some
“free” capacitive decoupling to the appropriate ground plane. It
is essential that care be taken in the layout of signal and power
ground interconnects to avoid inducing extraneous voltage
drops in the signal ground paths. It is recommended that all
connections be short, direct and as physically close to the pack-
age as possible to minimize the sharing of conduction paths
between different currents. When runs exceed an inch in length,
strip line techniques with proper termination resistor should be
considered. The necessity and value of this resistor will be de-
pendent upon the logic family used.
For a more detailed discussion of the implementation and con-
struction of high speed, mixed signal printed circuit boards,
refer to Analog Devices’ application notes AN-280 and AN-333.
TTL/CMOS
CIRCUITS
Figure 55. Differential LC Filter for Single +5 V or +3 V
Applications
LOGIC
POWER SUPPLY
+5V OR +3V
FERRITE
BEADS
100 F
ELECT.
10-22 F
TANT.
AD9760
0.1 F
CER.
AVDD
ACOM