AD5420AREZ Analog Devices Inc, AD5420AREZ Datasheet - Page 20

• Manufacturer Part Number: AD5420AREZ
• Description: IC DAC 16BIT 1CH SER 24TSSOP
• Manufacturer: Analog Devices Inc

Specifications of AD5420AREZ

• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Design Resources: Simplified 16-Bit, 4 mA-to-20 mA Output Solution Using AD5420 (CN0098)
• Settling Time: 10µs
• Number Of Bits: 16
• Number Of Converters: 1
• Voltage Supply Source: Analog and Digital
• Power Dissipation (max): 950mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-TSSOP Exposed Pad, 24-eTSSOP, 24-HTSSOP
• Resolution (bits): 16bit
• Input Channel Type: Serial
• Supply Voltage Range - Digital: 2.7V To 5.5V
• Supply Current: 4mA
• Digital Ic Case Style: TSSOP
• No. Of Pins: 24
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD5410/AD5420
AD5410/AD5420 FEATURES
FAULT ALERT
The AD5410/AD5420 are equipped with a FAULT pin, which is
an open-drain output allowing several AD5410/AD5420
devices to be connected together to one pull-up resistor for
global fault detection. The FAULT pin is forced active by any
one of the following fault scenarios:
•
•
The I
in conjunction with the FAULT pin to inform the user which
fault condition caused the FAULT pin to be asserted. See Table 17
and Table 15.
ASYNCHRONOUS CLEAR (CLEAR)
CLEAR is an active high clear that clears the current output to
the bottom of its programmed range. It is necessary to maintain
CLEAR high for a minimum amount of time (see Figure 2) to
complete the operation. When the CLEAR signal is returned
low, the output remains at the cleared value. The preclear value
can be restored by pulsing the LATCH signal low without
clocking any data. A new value cannot be programmed until the
CLEAR pin is returned low.
INTERNAL REFERENCE
The AD5410/AD5420 contain an integrated +5 V voltage
reference with initial accuracy of ±5 mV maximum and a
temperature drift coefficient of 10 ppm/°C maximum. The
reference voltage is buffered and externally available for use
elsewhere within the system. See Figure 34 for a load regulation
graph of the integrated reference.
The voltage at I
range, due to an open-loop circuit or insufficient power
supply voltage. The I
transistor and internal amplifier, as shown in Figure 38.
The internal circuitry that develops the fault output avoids
using a comparator with window limits because this requires
an actual output error before the FAULT output becomes
active. Instead, the signal is generated when the internal
amplifier in the output stage has less than approximately
1 V of remaining drive capability (when the gate of the
output PMOS transistor nearly reaches ground). Thus, the
FAULT output activates slightly before the compliance limit is
reached. Because the comparison is made within the feed-
back loop of the output amplifier, the output accuracy is
maintained by its open-loop gain and an output error does
not occur before the FAULT output becomes active.
If the core temperature of the AD5410/AD5420 exceeds
approximately 150°C.
OUT
fault and overtemp bits of the status register are used
OUT
attempts to rise above the compliance
OUT
current is controlled by a PMOS
Rev. B | Page 20 of 28
EXTERNAL CURRENT SETTING RESISTOR
In Figure 38, R
voltage-to-current conversion circuitry. The stability of the
output current over temperature is dependent on the stability of
the value of R
can be connected from the R
ground; this improves the overall performance of the AD5410/
AD5420. The external resistor is selected via the control
register. See Table 14.
DIGITAL POWER SUPPLY
By default, the DV
5.5 V. Alternatively, via the DV
power supply can be output on the DV
power supply for other devices in the system or as a termination
for pull-up resistors. This facility offers the advantage of not
having to bring a digital supply across an isolation barrier. The
internal power supply is enabled by leaving the DV
pin unconnected. To disable the internal supply, DV
should be tied to 0 V. DV
of current. See Figure 27 for a load regulation graph.
EXTERNAL BOOST FUNCTION
The addition of an external boost transistor, as shown in Figure 40,
reduces the power dissipated in the AD5410/AD5420 by reducing
the current flowing in the on-chip output transistor (dividing it
by the current gain of the external circuit). A discrete NPN
transistor with a breakdown voltage, BV
can be used.
The external boost capability allows the AD5410/AD5420 to be
used at the extremes of the supply voltage, load current, and
temperature range. The boost transistor can also be used to
reduce the amount of temperature-induced drift in the part.
This minimizes the temperature-induced drift of the on-chip
voltage reference, which improves drift and linearity.
SET
AD5410/
AD5420
SET
Figure 40. External Boost Configuration
. An external precision 15 kΩ low drift resistor
is an internal sense resistor as part of the
CC
pin accepts a power supply of 2.7 V to
BOOST
I
CC
OUT
0.022µF
is capable of supplying up to 5 mA
SET
CC
pin of the AD5410/AD5420 to
SELECT pin, an internal 4.5 V
1kΩ
CC
CEO
pin for use as a digital
, greater than 40 V
MJD31C
2N3053
OR
R
L
CC
CC
SELECT
SELECT