AD7390ARZ Analog Devices Inc, AD7390ARZ Datasheet - Page 5

• Manufacturer Part Number: AD7390ARZ
• Description: IC DAC 12BIT 3V SRL-IN 8-SOIC
• Manufacturer: Analog Devices Inc

Specifications of AD7390ARZ

• Data Interface: Serial
• Settling Time: 60µs
• Number Of Bits: 12
• Number Of Converters: 1
• Voltage Supply Source: Single Supply
• Power Dissipation (max): 500µW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Resolution (bits): 12bit
• Sampling Rate: 17kSPS
• Input Channel Type: Serial
• Supply Voltage Range - Analog: 2.7V To 5.5V
• Supply Current: 55µA
• Digital Ic Case Style: SOIC
• Number Of Channels: 1
• Resolution: 12b
• Conversion Rate: 17KSPS
• Interface Type: SERIAL 3W SPI QSPI
• Single Supply Voltage (typ): 3/5V
• Dual Supply Voltage (typ): Not RequiredV
• Architecture: R-2R
• Power Supply Requirement: Single
• Output Type: Voltage
• Integral Nonlinearity Error: ±2LSB
• Single Supply Voltage (min): 2.7V
• Single Supply Voltage (max): 5.5V
• Dual Supply Voltage (min): Not RequiredV
• Dual Supply Voltage (max): Not RequiredV
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 8
• Package Type: SOIC N
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

CLK
↑
X
X
X
X
↑ = Positive logic transition.
X = Don’t care.
AD7390
AD7391
V
OUT
CLR
H
H
L
↑
↑
CLK
CLK
CLR
SDI
SDI
LD
LD
FS
ZS
MSB
B11
D11
MSB
B9
D9
Table II. AD7390 Serial Input Register Data Format, Data is Loaded in the MSB-First Format
Table III. AD7391 Serial Input Register Data Format, Data is Loaded in the MSB-First Format
LD
H
L
X
H
L
B10
D10
t
LD1
D11
AD7390
B8
D8
Serial Shift Register Function
Shift-Register-Data Advanced One-Bit
Disables
No Effect
No Effect
Disabled
D10
B9
D9
t
AD7391
LD1
B7
D7
D9
t
CL
t
B8
D8
DS
Table I. Control-Logic Truth Table
B6
D6
t
DH
D7
B7
D7
t
CH
B5
D5
B6
D6
D5
Updated with Current Shift Register Contents
Previous SR Contents Loaded (Avoid usage of CLR
DAC Register Function
Latched
Loaded with all Zeros
Latched with all Zeros
when LD is logic low, since SR data could be corrupted
if a clock edge takes place, while CLR returns high.)
t
B5
D5
B4
D4
LDW
D4
t
S
D3
B4
D4
B3
D3
DAC REGISTER LOAD
D2
ERROR BAND
0.1% FS
B3
D3
D1
B2
D2
B2
D2
AD7390/AD7391
D0
t
CLRW
t
S
t
LD2
B1
D1
B1
D1
LSB
B0
D0
LSB
B0
D0