AD5063BRMZ Analog Devices Inc, AD5063BRMZ Datasheet - Page 14

• Manufacturer Part Number: AD5063BRMZ
• Description: IC DAC 16BIT 2.7-5.5V 10-MSOP
• Manufacturer: Analog Devices Inc
• Series: nanoDAC™r

Specifications of AD5063BRMZ

• Data Interface: Serial, SPI™
• Settling Time: 4µs
• Number Of Bits: 16
• Number Of Converters: 1
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 10-MSOP, Micro10™, 10-uMAX, 10-uSOP
• Resolution (bits): 16bit
• Sampling Rate: 333kSPS
• Input Channel Type: Serial
• Supply Voltage Range - Analog: 2.7V To 5.5V
• Supply Current: 650µA
• Digital Ic Case Style: SOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power Dissipation (max): -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

AD5063
POWER-ON TO MIDSCALE
The AD5063 contains a power-on reset circuit that controls the
output voltage during power-up. The DAC register is filled with
the midscale code, and the output voltage is midscale until a
valid write sequence is made to the DAC. This is useful in
applications where it is important to know the state of the DAC
output while it is in the process of powering up.
SOFTWARE RESET
The device can be put into software reset by setting all bits in
the DAC register to 1; this includes writing 1s to Bits D23 to
D16, which is not the normal mode of operation. Note that the
SYNC interrupt command cannot be performed if a software
reset command is started.
POWER-DOWN MODES
The AD5063 contains four separate modes of operation. These
modes are software-programmable by setting two bits (DB17
and DB16) in the control register. Table 6 shows how the state
of the bits corresponds to the operating mode of the device.
Table 6. Modes of Operation for the AD5063
When both bits are set to 0, the part has normal power con-
sumption. However, for the three power-down modes, the
supply current falls to 200 nA at 5 V (50 nA at 3 V). Not
only does the supply current fall, but the output stage is
also internally switched from the output of the amplifier to
a resistor network of known values. This has the advantage
that the output impedance of the part is known while the part
is in power-down mode. There are three options: The output
can be connected internally to GND through either a 1 kΩ
resistor or a 100 kΩ resistor, or it can be left open-circuited
(three-stated). The output stage is illustrated in Figure 29.
DB17
0
0
1
1
SYNC
SCLK
DIN
SYNC HIGH BEFORE 24
DB16
0
1
0
1
DB23
INVALID WRITE SEQUENCE:
Operating Mode
Normal operation
Power-down mode:
Three-state
100 kΩ to GND
1 kΩ to GND
TH
FALLING EDGE
DB0
Figure 31. SYNC Interrupt Facility
Rev. C | Page 14 of 20
The bias generator, DAC core, and other associated linear
circuitry are all shut down when the power-down mode is
activated. However, the contents of the DAC register are unaffected
when in power-down. The time to exit power-down is typically
2.5 μs for V
MICROPROCESSOR INTERFACING
AD5063 to ADSP-2101/ADSP-2103 Interface
Figure 30 shows a serial interface between the AD5063 and the
ADSP-2101/ADSP-2103. The ADSP-2101/ADSP-2103 should
be set up to operate in the SPORT transmit alternate framing
mode. The ADSP-2101/ADSP-2103 SPORT are programmed
through the SPORT control register and should be configured
as follows: internal clock operation, active low framing, and
16-bit word length. Transmission is initiated by writing a word
to the Tx register after the SPORT has been enabled.
1
ADDITIONAL PINS OMITTED FOR CLARITY
OUTPUT UPDATES ON THE 24
ADSP-2103
ADSP-2101/
Figure 30. AD5063 to ADSP-2101/ADSP-2103 Interface
DB23
AD5063
DD
VALID WRITE SEQUENCE:
DAC
Figure 29. Output Stage During Power-Down
= 5 V, and 5 μs for V
1
SCLK
TFS
DT
POWER-DOWN
CIRCUITRY
TH
FALLING EDGE
DB0
DD
= 3 V (see Figure 19).
SYNC
DIN
SCLK
RESISTOR
NETWORK
AD5063
V
OUT