AD5551BRZ Analog Devices Inc, AD5551BRZ Datasheet - Page 15

• Manufacturer Part Number: AD5551BRZ
• Description: IC DAC 14BIT SERIAL-IN 8-SOIC
• Manufacturer: Analog Devices Inc

Specifications of AD5551BRZ

• Data Interface: Serial
• Settling Time: 1µs
• Number Of Bits: 14
• Number Of Converters: 1
• Voltage Supply Source: Single Supply
• Power Dissipation (max): 6.05mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Resolution (bits): 14bit
• Sampling Rate: 1MSPS
• Input Channel Type: Serial
• Supply Voltage Range - Analog: 2.7V To 5.5V
• Supply Current: 300µA
• Digital Ic Case Style: SOIC
• Number Of Channels: 1
• Resolution: 14b
• Interface Type: Serial (3-Wire, SPI, QSPI, Microwire)
• Single Supply Voltage (typ): 3/5V
• Dual Supply Voltage (typ): Not RequiredV
• Architecture: R-2R
• Power Supply Requirement: Single
• Output Type: Voltage
• Integral Nonlinearity Error: ±1LSB
• Single Supply Voltage (min): 2.7V
• Single Supply Voltage (max): 5.5V
• Dual Supply Voltage (min): Not RequiredV
• Dual Supply Voltage (max): Not RequiredV
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 8
• Package Type: SOIC N
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

APPLICATIONS INFORMATION
OPTOCOUPLER INTERFACE
The digital inputs of the AD5551/AD5552 are Schmitt-
triggered, so they can accept slow transitions on the digital
input lines. This makes these parts ideal for industrial applica-
tions where it may be necessary that the DAC is isolated from
the controller via optocouplers. Figure 29 illustrates such an
interface.
POWER
SCLK
DIN
CS
Figure 29. AD5551/AD5552 in an Optocoupler Interface
10kΩ
10kΩ
10kΩ
V
V
V
DD
DD
DD
REGULATOR
SCLK
CS
DIN
5V
AD5551/
AD5552
GND
V
DD
V
OUT
10µF
0.1µF
Rev. A | Page 15 of 16
DECODING MULTIPLE AD5551/AD5552S
The CS pin of the AD5551/AD5552 can be used to select one of
a number of DACs. All devices receive the same serial clock and
serial data, but only one device receives the CS signal at any one
time. The DAC addressed is determined by the decoder. There
is some digital feedthrough from the digital input lines. Using a
burst clock minimizes the effects of digital feedthrough on the
analog signal channels.
ADDRESS
ENABLE
CODED
SCLK
DIN
Figure 30. Addressing Multiple AD5551/AD5552s
EN
DECODER
DGND
V
DD
Figure 30
shows a typical circuit.
AD5551/AD5552
CS
DIN
SCLK
CS
DIN
SCLK
CS
DIN
SCLK
CS
DIN
SCLK
AD5551/
AD5551/
AD5551/
AD5551/
AD5552
AD5552
AD5552
AD5552
V
V
V
V
OUT
OUT
OUT
OUT