AD7541AJP-REEL Analog Devices Inc, AD7541AJP-REEL Datasheet - Page 4

• Manufacturer Part Number: AD7541AJP-REEL
• Description: IC DAC 12BIT MULT MONO 20-PLCC
• Manufacturer: Analog Devices Inc

Specifications of AD7541AJP-REEL

• Rohs Status: RoHS non-compliant
• Settling Time: 600ns
• Number Of Bits: 12
• Data Interface: Parallel
• Number Of Converters: 1
• Voltage Supply Source: Single Supply
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 20-PLCC
• Power Dissipation (max): -

AD7541A
GENERAL CIRCUIT INFORMATION
The simplified D/A circuit is shown in Figure 1. An inverted
R-2R ladder structure is used—that is, the binarily weighted
currents are switched between the OUT1 and OUT2 bus lines,
thus maintaining a constant current in each ladder leg indepen-
dent of the switch state.
The input resistance at V
(R
value “R”). Since R
terminal can be driven by a reference voltage or a reference
current, ac or dc, of positive or negative polarity. (If a current
source is used, a low temperature coefficient external R
recommended to define scale factor.)
EQUIVALENT CIRCUIT ANALYSIS
The equivalent circuits for all digital inputs LOW and all digital
inputs HIGH are shown in Figures 2 and 3. In Figure 2 with all
digital inputs LOW, the reference current is switched to OUT2.
The current source I
tion leakages to the substrate, while the I/
represents a constant 1-bit current drain through the termina-
tion resistor on the R-2R ladder. The ON capacitance of the
output N-channel switch is 200 pF, as shown on the OUT2
terminal. The OFF switch capacitance is 70 pF, as shown on
the OUT1 terminal. Analysis of the circuit for all digital inputs
HIGH, as shown in Figure 3 is similar to Figure 2; however, the
ON switches are now on terminal OUT1, hence the 200 pF at
that terminal.
Figure 2. DAC Equivalent Circuit All Digital Inputs LOW
Figure 3. DAC Equivalent Circuit All Digital Inputs HIGH
LDR
V
REF
is the R/2R ladder characteristic resistance and is equal to
V
V
REF
REF
Figure 1. Functional Diagram (Inputs HIGH)
BIT 1 (MSB)
R
R
I
I
REF
REF
20k
DIGITAL INPUTS (DTL/TTL/CMOS COMPATIBLE)
15k
15k
S1
10k
LOGIC: A SWITCH IS CLOSED TO I
ITS DIGITAL INPUT IN A "HIGH" STATE.
BIT 2
IN
LEAKAGE
at the V
20k
S2
10k
I
I
/4096
/4096
REF
BIT 3
(Figure 1) is always equal to R
is composed of surface and junc-
20k
REF
S3
I
I
I
I
LEAKAGE
LEAKAGE
LEAKAGE
LEAKAGE
pin is constant, the reference
10k
BIT 12 (LSB)
20k
OUT1
S12
4096
200pF
200pF
70pF
70pF
FOR
current source
R
R
10k
20k
OUT2
OUT1
R
FEEDBACK
RFB
OUT1
OUT2
RFB
OUT1
OUT2
FB
is
LDR
–4–
APPLICATIONS
UNIPOLAR BINARY OPERATION
(2-QUADRANT MULTIPLICATION)
Figure 4 shows the analog circuit connections required for uni-
polar binary (2-quadrant multiplication) operation. With a dc
reference voltage or current (positive or negative polarity) ap-
plied at Pin 17, the circuit is a unipolar D/A converter. With an
ac reference voltage or current, the circuit provides 2-quadrant
multiplication (digitally controlled attenuation). The input/
output relationship is shown in Table II.
R1 provides full-scale trim capability [i.e., load the DAC register
to 1111 1111 1111, adjust R1 for V
Alternatively, Full Scale can be adjusted by omitting R1 and R2
and trimming the reference voltage magnitude.
C1 phase compensation (10 pF to 25 pF) may be required for
stability when using high speed amplifiers. (C1 is used to cancel
the pole formed by the DAC internal feedback resistance and
output capacitance at OUT1).
Amplifier A1 should be selected or trimmed to provide V
10% of the voltage resolution at V
fier should exhibit a bias current which is low over the tempera-
ture range of interest (bias current causes output offset at V
equal to I
The AD544L is a high speed implanted FET input op amp with
low factory-trimmed V
Binary Number in DAC
MSB
1 1 1 1
1 0 0 0
0 0 0 0
0 0 0 0
Table II. Unipolar Binary Code Table for Circuit of Figure 4
Table I. Recommended Trim Resistor Values vs. Grades
V
IN
B
R1
1 1 1 1
0 0 0 0
0 0 0 0
0 0 0 0
times the DAC feedback resistance, nominally 11 k ).
*
Trim
Resistor
R1
R2
Figure 4. Unipolar Binary Operation
17
BIT 1 – BIT 12
PINS 4–15
V
REF
V
V
16
DD
DD
OS
LSB
1 1 1 1
0 0 0 0
0 0 0 1
0 0 0 0
AD7541A
JN/AQ/SD
100
47
.
DGND
R
18
FB
OUT1
OUT2
3
OUT
DIGITAL
GROUND
OUT
R2
Analog Output, V
–V
–V
–V
0 Volts
*
. Additionally, the ampli-
KN/BQ/TD
100
33
1
2
IN
IN
IN
*
= –V
REFER TO TABLE 1
4095
4096
2048
4096
4096
REF
C1
33pF
ANALOG
COMMON
1
(4095/4096)].
AD544L
(SEE TEXT)
= –1/2 V
OUT
REV. B
OS
V
OUT
OUT
IN